t27 TxOH Data Hold time from rising edge of T" />
參數(shù)資料
型號: XRT72L71IQ
廠商: Exar Corporation
文件頁數(shù): 25/102頁
文件大?。?/td> 0K
描述: IC FRAMER DS3 ATM UNI 160PQFP
產(chǎn)品變化通告: XRT72Lx Series Obsolescence 02/May/2012
標(biāo)準(zhǔn)包裝: 24
控制器類型: DS3 ATM UNI,透明通道調(diào)幀器
電源電壓: 3.3V
電流 - 電源: 120mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 160-BQFP
供應(yīng)商設(shè)備封裝: 160-PQFP(28x28)
包裝: 托盤
á
XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
25
t27
TxOH Data Hold time from rising edge
of TxOHClk signal
0ns
t28
TxOHIns signal setup time to rising
edge of TxOHClk
11
ns
t29
TxOHIns signal hold time from rising
edge of TxOHClk
0ns
Transmit DS3 Framer (LIU Interface Port)—See Figure 8 and Figure 9
t30
Delay time of data on TxPOS or TxNEG,
following the rising edge of the
TxLineClk
0.7
2.0
ns
Transmit DS3 Framer is config-
ured to update TxPOS and
TxNEG on the rising edge of
TxLineClk.
t31
Delay time of data on TxPOS or
TxNEG following the falling edge
of the TxLineClk
0.7
1.5
ns
Transmit DS3 Framer is config-
ured to update TxPOS and
TxNEG on the falling edge of
TxLineClk.
fTxLineClk
Clock frequency of TxLineClk
44.736
MHz
t32
Period of TxLineClk clock signal
10
ns
t33
Bit Period of data on TxPOS or
TxNEG pins
10
ns
Receive DS3 Framer (Serial Output Port)—See Figure 10
fRxOHClk
Frequency of RxOHClk signal
526.3
kHz
t34
Period of RxOHClk clock signal
1900
ns
t35
Delay Time from rising edge of
RxOHClk to RxOHFrame signal
950
970
ns
>0.5 t34
t36
Delay Time from rising edge of
RxOHClk to valid data at RxOH
950
970
ns
>0.5 t34
t37
Bit Period of data at RxOH
1900
ns
Receive DS3 Framer (LIU Interface Port)—See Figure 11 and Figure 12
t38
RxPOS/RxNEG data Setup Time to
rising edge of RxLineClk
6ns
Receive DS3 Framer is configured
to sample RxPOS and RxNEG
on the rising edge of RxLineClk.
t39
RxPOS/RxNEG data Hold Time from
rising edge of RxLineClk
3ns
Receive DS3 Framer is configured
to sample RxPOS and RxNEG
on the rising edge of RxLineClk.
t40
RxPOS/RxNEG data Setup Time to
falling edge of RxLineClk
6ns
Receive DS3 Framer is configured
to sample RxPOS and RxNEG
on the falling edge of RxLineClk.
t41
RxPOS/RxNEG data Hold Time from
falling edge of RxLineClk
3
ns
Receive DS3 Framer is configured
to sample RxPOS and RxNEG
on the falling edge of RxLineClk.
fRxLineClk
Clock frequency of RxLineClk
44.736
MHz
t42
Period of RxLineClk clock signal
10
ns
AC ELECTRICAL CHARACTERISTICS (CONTINUED)
Test Conditions: TA = 25°C, VDD = 3.3V ± 5% unless otherwise specified
SYMBOL
PARAMETER
MIN.TYP.MAX.UNITS
CONDITIONS
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