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| 型號(hào)： | XRT72L71IQ |
| 廠商： | Exar Corporation |
| 文件頁(yè)數(shù)： | 42/102頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FRAMER DS3 ATM UNI 160PQFP |
| 產(chǎn)品變化通告： | XRT72Lx Series Obsolescence 02/May/2012 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 控制器類型： | DS3 ATM UNI，透明通道調(diào)幀器 |
| 電源電壓： | 3.3V |
| 電流 - 電源： | 120mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 160-BQFP |
| 供應(yīng)商設(shè)備封裝： | 160-PQFP（28x28） |
| 包裝： | 托盤 |
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XRT72L71
á
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
40
and insert a PRBS pattern into the DS3 payload
bits.
The PRBS receiver will receive these DS3 frames,
and will attempt to acquire “PRBS Lock” with this
DS3 frame data. Additionally, the PRBS Receiver
will report the occurrence of any errors by incre-
menting an on-chip register.
LINE INTERFACE DRIVE AND SCAN SECTION
The Line Interface Drive and Scan Section allows the
user to monitor and control many aspects of the
XRT7300 E3/DS3/STS-1 Line Interface Unit, via on-
chip registers, within the UNI IC. This feature elimi-
nates the need for glue logic to interface the
XRT72L71 DS3 UNI/Framer to the XRT7300 DS3 Line
Interface Unit IC.
The On-Chip Line Interface Drive register allows
the user to control the state of 6 output pins. The
function of these output pins, when asserted, are
tabulated below.
CLEAR CHANNEL MODE OPERATION
Signal Name
Function of Output Pin
Req
Receive Equalizer By-Pass:
“1” configures the XRT7300 to shut off its internal Receive Equalizer.
“0” configures the XRT7300 to enable its internal Receive Equalizer.
TAOS
Transmit “All Ones” Pattern.
“1” configures the XRT7300 LIU IC to overwrite the DS3 data that is output via the TxPOS and out-
puts, and transmit an “All Ones” pattern onto the line.
“0” configures the XRT7300 LIU IC to transmit data, as is applied to it via the TPDATA and TNDATA
input pins.
EncoDis
B3ZS Encoder Disable/Enable Select.
"1" disables the B3ZS Encoder, within the XRT7300.
"0" enables the B3ZS Decoder within the XRT7300.
TxLev
Transmit Output Signal Line Build Out Select.
Setting this bit-field to “1” disables the Transmit Line Build Out circuitry within the XRT7300. In this
case, the XRT7300 will generate an “unshaped” square wave signal out onto the line (via the TTIP and
TRING output pins).
Note: In order to configure the XRT7300 to generate a line signal that complies with the Transmit Output
Pulse Template Requirements (per Bellcore GR-499-CORE), this setting is advised if the cable length
between the Transmit Output of the XRT7300 and the DSX-3 Cross-Connect is greater than 225 feet.
Setting this bit-field to “0” enables the Transmit Line Build Out circuitry within the XRT7300. In this
case, the XRT7300 will generate a “shaped” square wave out onto the line (via the TTIP and TRING
output pins).
Note: In order to configure the XRT7300 to generate a line signal that complies with the Transmit Output
Pulse Template Requirements (per Bellcore GR-499-CORE), this setting is advised if the cable length
between the Transmit Output of the XRT7300 and the DSX-3 Cross-Connect is less than 225 feet.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT73L02MIV-F | IC LIU E3/DS3/STS-1 2CH 100TQFP |
| XRT73L03BIV-F | IC LIU E3/DS3/STS-1 3CH 120LQFP |
| XRT73L04BIV-F | IC LIU E3/DS3/STS-1 4CH 144LQFP |
| XRT73L06IB-F | IC LIU E3/DS3/STS-1 6CH 217BGA |
| XRT73LC00AIV-F | IC LIU STS1/DS3/E3 SGL 44TQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT72L71IQ-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Single CH DS3 UNI (3.3V) RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT72L73IB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| XRT72L74IB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| XRT7300 | 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT7300ES | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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