TABLE 102:
參數(shù)資料
型號： XRT72L71IQ
廠商： Exar Corporation
文件頁數(shù)： 94/102頁
文件大?。?/td> 0K
描述： IC FRAMER DS3 ATM UNI 160PQFP
產(chǎn)品變化通告： XRT72Lx Series Obsolescence 02/May/2012
標(biāo)準(zhǔn)包裝： 24
控制器類型： DS3 ATM UNI，透明通道調(diào)幀器
電源電壓： 3.3V
電流 - 電源： 120mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 160-BQFP
供應(yīng)商設(shè)備封裝： 160-PQFP（28x28）
包裝： 托盤
á
XRT72L71
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
87
TABLE 102: TX CP IDLE CELL PATTERN HEADER BYTE-2
REGISTER 101
TX CP IDLE CELL PATTERN HEADER BYTE-2
HEX ADDRESS: 0X65
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7-0
Tx Idle Cell Pattern 2
R/W
0x00
Contains pattern for the second header byte of each “outbound” idle cell.
Register is set to 0x00 when transmitting standard idle cell pattern.
NOTE: This bit-field is only active if the XRT72L71 is configured to operate
in the “ATM UNI” Mode.
TABLE 103: TX CP IDLE CELL PATTERN HEADER BYTE-3
REGISTER 102
TX CP IDLE CELL PATTERN HEADER BYTE-3
HEX ADDRESS: 0X66
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7-0
Tx Idle Cell Pattern 3
R/W
0x00
Contains pattern for the third header byte of each “outbound” idle cell.
Register is set to 0x00 when transmitting standard idle cell pattern.
NOTE: This bit-field is only active if the XRT72L71 is configured to operate
in the “ATM UNI” Mode.
TABLE 104: TX CP IDLE CELL PATTERN HEADER BYTE-4
REGISTER 103
TX CP IDLE CELL PATTERN HEADER BYTE-4
HEX ADDRESS: 0X67
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7-0
Tx Idle Cell Pattern 4
R/W
0x01
Contains pattern for the fourth header byte of each “outbound” idle cell.
Register is set to 0x01 when transmitting standard idle cell pattern.
NOTE: This bit-field is only active if the XRT72L71 is configured to operate
in the “ATM UNI” Mode.
TABLE 105: TX CP IDLE CELL PATTERN HEADER BYTE-5
REGISTER 104
TX CP IDLE CELL PATTERN HEADER BYTE-5
HEX ADDRESS: 0X68
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7-0
Tx Idle Cell Pattern 5
R/W
0x52
Contains pattern for the fifth header byte of each “outbound” idle cell.
Register is set to 0x00 when transmitting standard idle cell pattern.
NOTE: This bit-field is only active if the XRT72L71 is configured to operate
in the “ATM UNI” Mode.
TABLE 106: TX CP IDLE CELL PAYLOAD REGISTER
REGISTER 105
TX CP IDLE CELL PAYLOAD REGISTER
HEX ADDRESS: 0X69
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7-0
Tx Idle Cell Payload
R/W
0x5A
This register contains the value of the payload bytes within each “outbound”
Idle Cell. The contents of this register will be repeated 48 times, when filling
the payload of each “outbound” Idle Cell. pRegister is set to 0x5A when
transmitting standard idle cell pattern.
NOTE: This bit-field is only active if the XRT72L71 is configured to operate
in the “ATM UNI” Mode.
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