參數(shù)資料
型號(hào)： XRT72L71IQ
廠商： Exar Corporation
文件頁(yè)數(shù)： 11/102頁(yè)
文件大?。?/td> 0K
描述： IC FRAMER DS3 ATM UNI 160PQFP
產(chǎn)品變化通告： XRT72Lx Series Obsolescence 02/May/2012
標(biāo)準(zhǔn)包裝： 24
控制器類型： DS3 ATM UNI，透明通道調(diào)幀器
電源電壓： 3.3V
電流 - 電源： 120mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 160-BQFP
供應(yīng)商設(shè)備封裝： 160-PQFP（28x28）
包裝： 托盤
XRT72L71
á
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
12
75
RxUAddr3
I
Receive UTOPIA Address Bus input:
Please see description for RxUAddr4, pin 73.
NOTE: The user should tie this pin to “GND” whenever the XRT72L71 has
been configured to operate in the “Clear-Channel-Framer” Mode.
76
RxUClav
O
Receive UTOPIA—Cell Available: The Receive UTOPIA Interface block will
assert this output pin in order to indicate that the Rx FIFO has some ATM cell
data that needs to be read by the ATM Layer Processor. The exact functional-
ity of this pin depends upon whether the UNI is operating in the “Octet Level” or
“Cell Level” handshake mode.
Octet Level Handshaking Mode
When the Receive UTOPIA Interface block is operating in the “octet-level
handshaking” mode; this signal is asserted (toggles “High”) when at least one
byte of cell data exists within the RxFIFO (within the Receive UTOPIA Inter-
face block). This output pin will toggle “Low” if the RxFIFO is depleted of ATM
cell data.
Cell Level Handshaking Mode
When the Receive UTOPIA Interface block is operating in the “cell-level hand-
shaking” mode; this signal is asserted if the RxFIFO contains at least one full
cell of data. This signal will toggle “Low” if the RxFIFO is depleted of data, or if
it contains less than one full cell of data.
Multi-PHY Operation: When the UNI chip is operating in the Multi-PHY
mode, this signal will be tri-stated until the RxUClk cycle following the asser-
tion of a valid address on the Receive UTOPIA Address bus input pins (e.g., if
the contents on the Receive UTOPIA Address bus pins match that with the
Receive UTOPIA Address Register). Afterwards, this output pin will behave in
accordance with the cell-level handshake mode.
NOTE: This output pin is only active if the XRT72L71 has been configured to
operate in the “ATM UNI” Mode.
77
RxUAddr2
I
Receive UTOPIA Address Bus input:
Please see description for RxUAddr4, pin 73.
NOTE: The user should tie this pin to “GND” whenever the XRT72L71 has
been configured to operate in the “Clear-Channel-Framer” Mode.
78
VDD
****
Power Supply Pin
79
RxUAddr0
I
Receive UTOPIA Address Bus input - LSB:
Please see description for RxUAddr4, pin 73.
NOTE: The user should tie this pin to “GND” whenever the XRT72L71 has
been configured to operate in the “Clear-Channel Framer” Mode.
80
RxUAddr1
I
Receive UTOPIA Address Bus input:
Please see description for RxUAddr4, pin 73.
NOTE: The user should tie this pin to “GND” whenever the XRT72L71 has
been configured to operate in the “Clear-Channel Framer” Mode.
81
RxUEn
I
Receive UTOPIA Interface—Output Enable: This active-”Low” input signal
is used to control the drivers of the Receive UTOPIA Data Bus. When this sig-
nal is “High” (negated) then the Receive UTOPIA Data Bus is tri-stated. When
this signal is asserted, then the contents of the byte or word that is at the “front
of the RxFIFO” will be “popped” and placed on the Receive UTOPIA Data bus
on the very next rising edge of RxUClk.
NOTE: The user should tie this pin to “GND” whenever the XRT72L71 has
been configured to operate in the “Clear-Channel-Framer” Mode.
PIN DESCRIPTION (CONTINUED)
PIN NO.
SYMBOL
TYPE
DESCRIPTION
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