參數(shù)資料
型號(hào): STPCI2EEYC
廠商: STMICROELECTRONICS
元件分類: 外設(shè)及接口
英文描述: MULTIFUNCTION PERIPHERAL, PBGA516
封裝: PLASTIC, BGA-516
文件頁(yè)數(shù): 8/80頁(yè)
文件大?。?/td> 854K
代理商: STPCI2EEYC
STRAP OPTION
Issue 0.4 - July 16, 2001
16/80
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
2.1.3. HCLK PLL STRAP REGISTER
Table 2-1. HCLK Frequency Programming
HCLK_STRAP0
Access = 0022h/0023h
Regoffset =05Fh
7
6543210
MD[3]
MD[2]
MD[26]
MD[25]
MD[24]
Rsv
This register defaults to the values sampled on the MD pins after reset
Bit Number Sampled
Mnemonic
Description
Bits 7-3
MD[3:2] & MD[26:24]
These pins reflect the values sampled on MD[3:2] and MD[26:24] pins re-
spectively and control the Host clock frequency synthesizer as shown in
Table 2-1
Bits 2-0
Rsv
Reserved
MD[3]
MD[2]
MD[26]
MD[25]
MD[24]
HCLK Speed
0000
0
25 MHz
0000
1
50 MHz
0001
0
60 MHz
0001
1
66 MHz
0100
1
75 MHz
1001
1
90 MHz
1100
1
100 MHz
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