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參數(shù)資料
| 型號： | STPCI2EEYC |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 外設及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PBGA516 |
| 封裝： | PLASTIC, BGA-516 |
| 文件頁數(shù)： | 25/80頁 |
| 文件大?。?/td> | 854K |
| 代理商： | STPCI2EEYC |
PIN DESCRIPTION
31/80
Issue 0.4 - July 16, 2001
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PCS1#, PCS3#
Primary Chip Select. These sig-
nals are used as the active high primary master &
slave IDE chip select signals. These signals must
be externally ANDed with the ISAOE# signal be-
fore driving the IDE devices to guarantee it is ac-
tive only when ISA bus is idle.
SCS1#, SCS3# Secondary Chip Select. These
signals are used as the active high secondary
master & slave IDE chip select signals. These sig-
nals must be externally ANDed with the ISAOE#
signal before driving the IDE devices to guarantee
it is active only when ISA bus is idle.
DIORDY
Busy/Ready. This pin serves as IDE sig-
nal DIORDY.
PIRQ Primary Interrupt Request.
SIRQ
Secondary Interrupt Request.
Interrupt request from IDE channels.
PDRQ Primary DMA Request.
SDRQ
Secondary DMA Request.
DMA request from IDE channels.
PDACK# Primary DMA Acknowledge.
SDACK# Secondary DMA Acknowledge.
DMA acknowledge to IDE channels.
PDIOR#, PDIOW# Primary I/O Read & Write.
SDIOR#, SDIOW# Secondary I/O Read & Write.
Primary & Secondary channel read & write.
3.3.9 MONITOR INTERFACE
RED, GREEN, BLUE RGB Video Outputs. These
are the 3 analog colour outputs from the RAM-
DACs. These signals are sensitive to interference,
therefore they need to be properly shielded.
VSYNC
Vertical Synchronisation Pulse. This is
the vertical synchronization signal from the VGA
controller.
HSYNC Horizontal Synchronisation Pulse.This is
the horizontal synchronization signal from the
VGA controller.
VREF_DAC DAC Voltage reference. This pin is
an input driving the digital to analog converters.
This allows an external voltage reference source
to be used.
RSET
Resistor Current Set. This is the reference
current input to the RAMDAC. Used to set the full-
scale output of the RAMDAC.
COMP
Compensation. This is the RAMDAC com-
pensation pin. Normally, an external capacitor
(typically 10nF) is connected between this pin and
VDD to damp oscillations.
DDC[1:0]
Direct Data Channel Serial Link.These
bidirectional pins are connected to CRTC register
3Fh to implement DDC capabilities. They conform
to I
2C electrical specifications, they have open-
collector output drivers which are internally con-
nected to VDD through pull-up resistors.
They can instead be used for accessing I C devic-
es on board. DDC1 and DDC0 correspond to SCL
and SDA respectively.
3.3.10 VIDEO INTERFACE
VCLK
Pixel Clock Input.This signal is used to syn-
chronise data being transferred from an external
video device to either the frame buffer, or alterna-
tively out the TV output in bypass mode. This pin
can be sourced from STPC if no external VCLK is
detected, or can be input from an external video
clock source.
VIN[7:0] YUV Video Data Input ITU-R 601 or 656.
Time multiplexed 4:2:2 luminance and chromi-
nance data as defined in ITU-R Rec601-2 and
Rec656 (except for TTL input levels). This bus typ-
ically carries a stream of Cb,Y,Cr,Y digital video at
VCLK frequency, clocked on the rising edge (by
default) of VCLK.
VCS Line synchronisation Input. This is the hori-
zontal synchronisation of the incomming CCIR601
video.
The signal is synchronous to rising edge of VCLK.
ODD_EVEN Frame Synchronisation Output.This
is the vertical synchronisation of the incomming
CCIR601 video.
The signal is synchronous to rising edge of VCLK.
The default polarity for this pin is:
- odd (not-top) field: LOW level
- even (bottom) field: HIGH level
3.3.11 TFT INTERFACE SIGNALS
The TFT (Thin Film Transistor) interface converts
signals from the CRT controller into control signals
for an external TFT Flat Panel. The signals are
listed below.
TFTFRAME,
Vertical Sync. pulse Output.
TFTLINE, Horizontal Sync. Pulse Output.
TFTDE,
Data Enable.
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