參數(shù)資料
型號： STPCI2EEYC
廠商： STMICROELECTRONICS
元件分類： 外設(shè)及接口
英文描述： MULTIFUNCTION PERIPHERAL, PBGA516
封裝： PLASTIC, BGA-516
文件頁數(shù)： 19/80頁
文件大?。?/td> 854K
代理商： STPCI2EEYC
PIN DESCRIPTION
Issue 0.4 - July 16, 2001
26/80
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
3.2. SIGNAL DESCRIPTIONS
3.3.1 BASIC CLOCKS AND RESETS
SYSRSTI# System Reset/Power good. This input
is low when the reset switch is depressed. Other-
wise, it reflects the power supply’s power good
signal. PWGD is asynchronous to all clocks, and
acts as a negative active reset. The reset circuit
initiates a hard reset on the rising edge of PWGD.
Note that while Reset is being asserted, the sig-
nals on the device pins are in an unknown state.
SYSRSTO#
Reset Output to System. This is the
system reset signal and is used to reset the rest of
the components (not on Host bus) in the system.
The ISA bus reset is an externally inverted buff-
ered version of this output and the PCI bus reset is
an externally buffered version of this output.
XTALI
14.3 MHz Crystal Input
XTALO 14.3 MHz Crystal Output. These pins are
provided for the connection of an external 14.318
MHz crystal to provide the reference clock for the
internal frequency synthesizer, from which the
HCLK and CLK24M signals are generated.
The 14.31818 MHz series-cut fundamental (not
overtone) mode quartz crystal must have an
Equivalent Series Resistance (ESR, sometimes
referred to as Rm) of less then 50 Ohms (typically
8 Ohms) and a shunt capacitance (Co) of less
than 7 pF. Balance capacitors of 16 pF should
also be added, one connected to each pin.
In the event of an external oscillator providing the
master clock signal to the STPC Atlas device, the
TTL signal should be connected to XTALI.
PCI_CLKI
33 MHz PCI Input Clock. This signal
must be connected to a clock generator and is
usually connected to PCI_CLKO.
PCI_CLKO
33 MHz PCI Output Clock.This is the
master PCI bus clock output
ISA_CLK
ISA Clock Output (also Multiplexer Se-
lect Line For IPC). This pin produces the Clock
signal for the ISA bus. It is also used with
ISA_CLK2X as the multiplexer control lines for the
Interrupt Controller Interrupt input lines. This is a
divided down version of the PCICLK or OSC14M.
ISA_CLKX2
ISA Clock Output (also Multiplexer
Select Line For IPC).This pin produces a signal at
twice the frequency of the ISA bus Clock signal. It
is also used with ISA_CLK as the multiplexer con-
trol lines for the Interrupt Controller Interrupt input
lines.
CLK14M
ISA bus synchronisation clock. This is
the buffered 14.318 MHz clock to the ISA bus.
This clock also provides the reference clock to the
frequency synthesizer that generates GCLK2X
and DCLK.
HCLK Host Clock. This is the host 1X clock. Its
frequency can vary from 50 to 75 MHz. All host
transactions and PCI transactions are synchro-
nized to this clock. Host transactions executed by
the DRAM controller are also driven by this clock.
DEV_CLK
24 MHz Peripheral Clock (floppy
drive). This 24 MHz signal is provided as a con-
venience for the system integration of a Floppy
Disk driver function in an external chip.This clock
signal is not available in Local Bus mode.
DCLK
135 MHz Dot Clock. This is the dot clock,
which drives graphics display cycles. Its frequency
can be as high as 135 MHz, and it is required to
have a worst case duty cycle of 60-40. For further
details, refer to Section 2.1.4. bit 4.
3.3.2 MEMORY INTERFACE
MCLKI
Memory Clock Input. This clock is driving
the SDRAM controller, the graphics engine and
display controller. This input should be a buffered
version of the MCLKO signal with the track lengths
between the buffer and the pin matched with the
track lengths between the buffer and the Memory
Banks.
MCLKO
Memory Clock Output. This clock drives
the Memory Banks on board and is generated
from an internal PLL.
CS#[1:0] Chip Select These signals are used to
disable or enable device operation by masking or
enabling all SDRAM inputs except MCLK, CKE,
and DQM.
CS#[2]/MA[11]
Chip Select/Bank Address This
pin is CS#[2] in the case when 16-Mbit devices are
used. For all other densities, it becomes MA[11].
CS#[3]/MA[12]/BA[1] Chip Select/ Memory Ad-
dress/ Bank Address This pin is CS#[3] in the case
when 16 Mbit devices are used. For all other den-
sities, it becomes MA[12] when 2 internal banks
devices are used and BA[1] when 4 internal bank
devices are used.
MA[10:0]
Memory Address. Multiplexed row and
column address lines.
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