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參數(shù)資料
| 型號： | STPCI2EEYC |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PBGA516 |
| 封裝： | PLASTIC, BGA-516 |
| 文件頁數(shù)： | 67/80頁 |
| 文件大?。?/td> | 854K |
| 代理商： | STPCI2EEYC |
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GENERAL DESCRIPTION
7/80
Issue 0.4 - July 16, 2001
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
trolled Chip Power Down, together with further
controls for 3.3V suspend with Modem Ring
Resume Detection.
The need for system configuration jumpers is
eliminated by providing address mapping support
for PCMCIA 2.0 / JEIDA 4.1 PC-Card memory to-
gether with address windowing support for I/O
space.
The STPC Atlas implements a multi-function par-
allel port. The standard PC/AT compatible logical
address assignments for LPT1, LPT2 and LPT3
are supported.
The parallel port can be configured for any of the
following three modes and supports the IEEE
Standard 1284 parallel interface protocol stand-
ards, as follows:
- Compatibility Mode (Forward channel, standard)
- Nibble Mode (Reverse channel, PC compatible)
- Byte Mode (Reverse channel, PS/2 compatible)
The STPC Atlas BGA package has 516 balls. This
however is not sufficient for all of the integrated
functions available; some features therefore share
the same balls and cannot thus be used at the
same time. The STPC Atlas configuration is done
by ‘strap options’. This is a set of pull-up or pull-
down resistors on the memory data bus, checked
on reset, which auto-configure the STPC Atlas.
There are three distinguishable
independently
configurable main blocks: The ISA block, the Lo-
cal Bus block and the PCI/PC Card block.
From the first two blocks, either the ISA bus and
some IPC additional features can be activated, or
alternatively, the Local bus, the parallel port and
the second serial interface.
From the third block, either the PCI bus can be ac-
tivated, or the PC Card interface (PCMCIA).
The STPC Atlas core is compliant with the Ad-
vanced Power Management (APM) specification
to provide a standard method by which the BIOS
can control the power used by personal comput-
ers. The Power Management Unit (PMU) module
controls the power consumption, providing a com-
prehensive set of features that controls the power
usage and supports compliance with the United
States Environmental Protection Agency’s Energy
Star Computer Program. The PMU provides the
following hardware structures to assist the soft-
ware in managing the system power consumption:
- System Activity Detection.
- Three power-down timers detecting system inac-
tivity:
- Doze timer (short durations).
- Stand-by timer (medium durations).
- Suspend timer (long durations).
- House-keeping activity detection.
- House-keeping timer to cope with short bursts of
house-keeping activity while dozing or in stand-by
state.
- Peripheral activity detection.
- Peripheral timer detecting peripheral inactivity
- SUSP# modulation to adjust the system perform-
ance in various power down states of the system
including full power-on state.
- Power control outputs to disable power from dif-
ferent planes of the board.
Lack of system activity for progressively longer
periods of time is detected by the three power
down timers. These timers can generate SMI in-
terrupts to CPU so that the SMM software can put
the system in decreasing states of power con-
sumption. Alternatively, system activity in a power
down state can generate an SMI interrupt to allow
the software to bring the system back up to full
power-on state. The chip-set supports up to three
power down states described above; these corre-
spond to decreasing levels of power savings.
Power down puts the STPC Atlas into suspend
mode. The processor completes execution of the
current instruction, any pending decoded instruc-
tions and associated bus cycles. During the sus-
pend mode, internal clocks are stopped. Remov-
ing power-down, the processor resumes instruc-
tion fetching and begins execution in the instruc-
tion stream at the point it had stopped. Because of
the static nature of the core, no internal data is
lost.
An industry standard EIDE (ATA 2) controller is
built in to the STPC Atlas and connected internally
via the PCI bus.
The STPC Atlas has three additional features;
USB, GPIO and JTAG. These are described brief-
ly below.
Universal Serial Bus (USB) is a general purpose
communications interface for connecting peripher-
als to a PC. The USB Open Host Controller Inter-
face (Open HCI) Specification, revision 1.1, sup-
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| STPCI2GDY | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:X86 Core PC Compatible System-on-Chip for Terminals |
| STPCI2GDYI | 功能描述:微處理器 - MPU 120MHz x86 SoC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| STPCI2GDYIE | 制造商:STMicroelectronics 功能描述: |
| STPCI2HDYC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PERIPHERAL (MULTIFUNCTION) CONTROLLER |
| STPCI2HEYC | 功能描述:微處理器 - MPU 133MHz x86 SoC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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