參數(shù)資料
型號： STPCI2EEYC
廠商： STMICROELECTRONICS
元件分類： 外設(shè)及接口
英文描述： MULTIFUNCTION PERIPHERAL, PBGA516
封裝： PLASTIC, BGA-516
文件頁數(shù)： 23/80頁
文件大?。?/td> 854K
代理商： STPCI2EEYC
DESCRIPTION
3/80
Issue 0.4 - July 16, 2001
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
s
TFT Interface
s
Programmable panel size up to 1024 by 1024
pixels.
s
Support for VGA and SVGA active matrix
TFT flat panels with 9, 12, 18-bit interface (1
pixel per clock).
s
Support for XGA and SXGA active matrix
TFT flat panels with 2 x 9-bit interface (2
pixels per clock).
s
Programmable image positionning.
s
Programmable blank space insertion in text
mode.
s
Programmable horizontal and vertical image
expansion in graphic mode.
s
Two fully programmable PWM (Pulse Width
Modulator) signals to adjust the flat panel
brightness and contrast.
s
Supports PanelLink
TM
high speed serial
transmitter
externally
for high
resolution
panel interface.
s
PCI Controller
s
Compliant with PCI 2.1 specification.
s
Integrated PCI arbitration interface. Up to 3
masters can connect directly. External logic
allows for greater than 3 masters.
s
Translation of PCI cycles to ISA bus.
s
Translation of ISA master initiated cycle to
PCI.
s
Support for burst read/write from PCI master.
s
PCI clock is 1/2, 1/3 or 1/4 CPU bus clock.
s
ISA master/slave
s
Generates the ISA clock from either
14.318MHz oscillator clock or PCI clock
s
Supports programmable extra wait state for
ISA cycles
s
Supports I/O recovery time for back to back
I/O cycles.
s
Fast Gate A20 and Fast reset.
s
Supports the single ROM that C, D, or E.
blocks shares with F block BIOS ROM.
s
Supports flash ROM.
s
Supports ISA hidden refresh.
s
Buffered DMA & ISA master cycles to reduce
bandwidth utilization of the PCI and Host bus.
s
Local Bus interface
s
Multiplexed with ISA/DMA interface.
s
Low latency asynchronous bus
s
16-bit data bus with word steering capability.
s
Programmable timing (Host clock granularity)
s
4 Programmable Flash Chip Select.
s
8 Programmable I/O Chip Select.
s
I/O device timing (setup & recovery time)
programmable
s
Supports 32-bit Flash burst.
s
2-level hardware key protection for Flash boot
block protection.
s
Supports 2 banks of 32MB flash devices with
boot block shadowed to 0x000F0000.
s
Reallocatable Memory space Windows
s
IDE Interface
s
Supports PIO
s
Transfer Rates to 22 MBytes/sec
s
Supports up to 4 IDE devices
s
Concurrent channel operation (PIO modes) -
4 x 32-Bit Buffer FIFOs per channel
s
Support for PIO mode 3 & 4.
s
Individual drive timing for all four IDE devices
s
Supports both legacy & native IDE modes
s
Supports hard drives larger than 528MB
s
Support for CD-ROM and tape peripherals
s
Backward compatibility with IDE (ATA-1).
s
Drivers for Windows and other Operating
Systems
s
Integrated Peripheral Controller
s
2X8237/AT compatible 7-channel DMA
controller.
s
2X8259/AT compatible interrupt Controller.
16 interrupt inputs - ISA and PCI.
s
Three 8254 compatible Timer/Counters.
s
Co-processor error support logic.
s
Supports external RTC (Not in Local Bus
Mode).
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