參數(shù)資料
型號(hào): STPCI2EEYC
廠商: STMICROELECTRONICS
元件分類: 外設(shè)及接口
英文描述: MULTIFUNCTION PERIPHERAL, PBGA516
封裝: PLASTIC, BGA-516
文件頁(yè)數(shù): 59/80頁(yè)
文件大?。?/td> 854K
代理商: STPCI2EEYC
BOARD LAYOUT
Issue 0.4 - July 16, 2001
62/80
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
5.3.3 Board Layout Issues
The physical layout of the motherboard PCB as-
sumed in this presentation is as shown inFigure
5-11. Because all of the memory interface signal
balls are located in the same region of the STPC
device, it is possible to orientate the device to re-
duce the trace lengths. The worst case routing
length to the DIMM1 is estimated to be 100mm.
Solid power and ground planes are a must in order
to provide good return paths for the signals and to
reduce EMI and noise. Also there should be ample
high frequency decoupling between the power
and ground planes to provide a low impedance
path between the planes for the return paths for
signal routings which change layers. If possible,
the traces should be routed adjacent to the same
power or ground plane for the length of the trace.
For the SDRAM interface, the most critical signal
is the clock. Any skew between the clocks at the
SDRAM components and the memory controller
will impact the timing budget. In order to get well
matched clocks at all components it is recom-
mended that all the DIMM clock pins, STPC mem-
ory clock input (MCLKI) and any other component
using the memory clock are individually driven
from a low skew clock driver with matched routing
lengths. This is shown in Figure 5-12.
Figure 5-11. DIMM placement
D IMM2
D IMM1
ST P C
35m m
15 m m
10 m m
116m m
S DRA M I/F
Figure 5-12. Clock Routing
MCL K O
D IM M C K n input
ST P C M C LK I
D IM M C K n input
Low s ke w c lo c k driv er:
L
L+ 75m m *
2 0pF
* N o additional 75m m w hen S DRA M direc tly s old er ed o n b oar d
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