參數(shù)資料
型號(hào): STPCI2EEYC
廠商: STMICROELECTRONICS
元件分類: 外設(shè)及接口
英文描述: MULTIFUNCTION PERIPHERAL, PBGA516
封裝: PLASTIC, BGA-516
文件頁(yè)數(shù): 36/80頁(yè)
文件大?。?/td> 854K
代理商: STPCI2EEYC
ELECTRICAL SPECIFICATIONS
41/80
Issue 0.4 - July 16, 2001
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
4.4 DC CHARACTERISTICS
Notes:
1. MHz ratings refer to CPU clock frequency.
2. Not yet released.
4.5 AC CHARACTERISTICS
Table
4-4 through Table
4-18 list the AC
characteristics
including
output delays, input
setup requirements, input hold requirements and
output float delays. These measurements are
based on the measurement points identified in
Figure 4-1. The rising clock edge reference level
VREF and other reference levels are shown in
Table 4-4 below for the STPC Atlas. Input or
output signals must cross these levels during
testing.
Figure 4-1 shows output delay (A and B) and
input setup and hold times (C and D). Input setup
and hold times (C and D) are specified minimums,
defining the smallest acceptable sampling window
a synchronous input signal must be stable for
correct operation.
Table 4-2. DC Characteristics
Recommended Operating conditions: VDD = 3.3 V
±0.3 V, Vcore =2.5 V + 0.2 V - 0.05 V, Tcase = 0 to
85
°C (Commercial Range) or -15 to 115°C (Industrial Range) unless otherwise specified.
Symbol
Parameter
Test condit ions
Min
Typ
Max
Unit
VDD
Operating Voltage
3.0
3.3
3.6
V
VCORE Operating Voltage
2.45
2.5
2.7
V
PDD
Supply Power
VDD=3.3 V, Vcore = 2.5 V + 0.2 V -
0.05 V, HCLK=133 MHz
2.0
2.6
W
HCLK
Internal Clock
(Note 1)
133
MHz
VDAC
DAC Voltage Reference
1.215
1.235
1.255
V
VOL
Output Low Voltage
ILoad =1.5 to 8mA depending of the pin
0.5
V
VOH
Output High Voltage
ILoad =-0.5 to -8mA depending of the pin
2.4
V
VILD
Input Low Voltage
Except XTALI
-0.3
0.8
V
XTALI
-0.3
0.5
V
VIHD
Input High Voltage
Except XTALI
2.1
VDD+0.3
V
XTALI
2.35
VDD+0.3
V
ILK
Input Leakage Current
Input, I/O
-5
5
A
CIN
Input Capacitance
(Note 2)
pF
COUT
Output Capacitance
(Note 2)
pF
CCLK
Clock Capacitance
(Note 2)
pF
Table 4-3. RAMDAC DC Specification
Symbol
Parameter
Min
Nom
Max
Vref
Voltage Reference
1.00 V
1.12 V
1.24 V
INL
Integrated Non Linear Error
-
2 lsb
DNL
Differentiated Non Linear Error
-
1lsb
FS
Full Scale
-
20mA
FSR
Full Scale Range
14.00 mA
16.50mA
19.00 mA
LSB
Least Significant Byte Size
54uA
63uA
72uA
Zero
Zero Scale @ 7.5IRE Mode
0.95mA
1.44mA
1.90mA
Compare
DAC to DAC matching
-
+/- 5%
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