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| 型號： | STPCI2EEYC |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PBGA516 |
| 封裝： | PLASTIC, BGA-516 |
| 文件頁數(shù)： | 22/80頁 |
| 文件大?。?/td> | 854K |
| 代理商： | STPCI2EEYC |
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PIN DESCRIPTION
29/80
Issue 0.4 - July 16, 2001
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
GPIOCS#
I/O General Purpose Chip Select 1.
This output signal is used by the external latch on
ISA bus to latch the data on the SD[7:0] bus. The
latch can be use by PMU unit to control the exter-
nal peripheral devices to power down or any other
desired function.
RTCRW# Real Time Clock RW#. This pin is used
as RTCRW#. This signal is asserted for any I/O
write to port 71h.
RTCDS# Real Time Clock DS. This pin is used as
RTCDS. This signal is asserted for any I/O read to
port 71h.
RTCAS#
Real time clock address strobe.This sig-
nal is asserted for any I/O write to port 70h.
RMRTCCS#
ROM/Real Time clock chip select.
This pin is a multi-function pin. This signal is as-
serted if a ROM access is decoded during a mem-
ory cycle. It should be combined with MEMR# or
MEMW# signals to properly access the ROM.
During an IO cycle, this signal is asserted if ac-
cess to the Real Time Clock (RTC) is decoded. It
should be combined with IOR# or IOW# signals to
properly access the real time clock.
IRQ_MUX[3:0] Multiplexed Interrupt Request.
These are the ISA bus interrupt signals. They are
to be encoded before connection to the STPC At-
las using ISACLK and ISACLKX2 as the input se-
lection strobes.
Note that IRQ8B, which by convention is connect-
ed to the RTC, is inverted before being sent to the
interrupt controller, so that it may be connected di-
rectly to the IRQ# pin of the RTC.
ISAOE#
Bidirectional OE Control.This signal con-
trols the OE signal of the external transceiver that
connects the IDE DD bus and ISA SA bus.
KBCS#
Keyboard Chip Select. This signal is as-
serted if a keyboard access is decoded during a I/
O cycle.
ZWS#
Zero Wait State. This signal, when assert-
ed by addressed device, indicates that current cy-
cle can be shortened.
DACK_ENC[2:0]
DMA Acknowledge. These are
the ISA bus DMA acknowledge signals. They are
encoded by the STPC Atlas before output and
should be decoded externally using ISACLK and
ISACLKX2 as the control strobes.
DREQ_MUX[1:0]
ISA Bus Multiplexed DMA Re-
quest. These are the ISA bus DMA request sig-
nals. They are to be encoded before connection to
the STPC Atlas using ISACLK and ISACLKX2 as
the input selection strobes.
TC
ISA Terminal Count. This is the terminal count
output of the DMA controller and is connected to
the TC line of the ISA bus. It is asserted during the
last DMA transfer, when the Byte count expires.
3.3.5 LOCAL BUS
PA[24:0]
Address Bus Output.
PD[15:0] Data Bus. This is the 16-bit data bus.
D[7:0] is the LSB and PD[15:8] is the MSB.
PWR#[1:0]
Write Control output. These are mem-
ory and I/O Write signals. PWR0# is used to write
the LSB and PWR1# to write the MSB.
PRD#[1:0]
Read Control output. These are mem-
ory and I/O Read signals. PRD0# is used to read
the LSB and PRD1# to read the MSB.
PRDY# Data Ready input. This signal is used to
create wait states on the bus. When low, it com-
pletes the current cycle.
FCS#[1:0] Two Flash Memory Chip Select out-
puts. These are the Programmable Chip Select
signals for Flash memory.
IOCS#[7:0] I/O Chip Select output. These are the
Programmable Chip Select signals for up to 4 ex-
ternal I/O devices.
PBE#[1:0] Peripheral Byte Enable. These are the
Byte enables that identifies on which databus the
date is valid. PBE#[0] corresponds to PD[7:0] and
PBE#[1] corresponds to PD[15:8]. These are nor-
mally used when 8 bit transfers are transfered
across the 16 bit bus.
IRQ_MUX#[3:0]
Multiplexed Interrupt Lines.
3.3.6 IPC
DACK_ENC[2:0]
DMA Acknowledge. These are
the ISA bus DMA acknowledge signals. They are
encoded by the STPC Industrial before output and
should be decoded externally using ISACLK and
ISACLKX2 as the control strobes.
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