參數(shù)資料
型號： STPCI2EEYC
廠商： STMICROELECTRONICS
元件分類： 外設(shè)及接口
英文描述： MULTIFUNCTION PERIPHERAL, PBGA516
封裝： PLASTIC, BGA-516
文件頁數(shù)： 21/80頁
文件大?。?/td> 854K
代理商： STPCI2EEYC
PIN DESCRIPTION
Issue 0.4 - July 16, 2001
28/80
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
3.3.4 ISA BUS INTERFACE
LA[23:17]
Unlatched Address. These unlatched
ISA Bus pins address bits 23-17 on 16-bit devices.
When the ISA bus is accessed by any cycle initiat-
ed from the PCI bus, these pins are in output
mode. When an ISA bus master owns the bus,
these pins are tristated.
SA[19:0]
Unlatched Address. These are the 20
low bits of the system address bus of ISA. These
pins are used as an input when an ISA bus master
owns the bus and are outputs at all other times.
SD[15:0]
I/O Data Bus (ISA). These are the exter-
nal ISA databus pins.
IOCHRDY IO Channel Ready. IOCHRDY is the IO
channel ready signal of the ISA bus and is driven
as an output in response to an ISA master cycle
targeted to the host bus or an internal register of
the STPC Atlas. The STPC Atlas monitors this sig-
nal as an input when performing an ISA cycle on
behalf of the host CPU, DMA master or refresh.
ISA masters which do not monitor IOCHRDY are
not guaranteed to work with the STPC Atlas since
the access to the system memory can be consid-
erably delayed due to CRT refresh or a write back
cycle.
ALE Address Latch Enable. This is the address
latch enable output of the ISA bus and is asserted
by the STPC Atlas to indicate that LA23-17, SA19-
0, AEN and SBHE# signals are valid. The ALE is
driven high during refresh, DMA master or an ISA
master cycles by the STPC Atlas.
ALE is driven low after reset.
BHE#
System Bus High Enable.This signal, when
asserted, indicates that a data Byte is being trans-
ferred on SD15-8 lines. It is used as an input when
an ISA master owns the bus and is an output at all
other times.
MEMR# Memory Read. This is the memory read
command signal of the ISA bus. It is used as an in-
put when an ISA master owns the bus and is an
output at all other times.
The MEMR# signal is active during refresh.
MEMW#
Memory Write. This is the memory write
command signal of the ISA bus. It is used as an in-
put when an ISA master owns the bus and is an
output at all other times.
SMEMR#
System Memory Read. The STPC Atlas
generates SMEMR# signal of the ISA bus only
when the address is below one MByte or the cycle
is a refresh cycle.
SMEMW#
System Memory Write. The STPC At-
las generates SMEMW# signal of the ISA bus only
when the address is below one MByte.
IOR# I/O Read. This is the IO read command sig-
nal of the ISA bus. It is an input when an ISA mas-
ter owns the bus and is an output at all other
times.
IOW#
I/O Write. This is the IO write command sig-
nal of the ISA bus. It is an input when an ISA mas-
ter owns the bus and is an output at all other
times.
MASTER#
Add On Card Owns Bus.This signal is
active when an ISA device has been granted bus
ownership.
MCS16#
Memory Chip Select16. This is the de-
code of LA23-17 address pins of the ISA address
bus without any qualification of the command sig-
nal lines. MCS16# is always an input. The STPC
Atlas ignores this signal during IO and refresh cy-
cles.
IOCS16# IO Chip Select16. This signal is the de-
code of SA15-0 address pins of the ISA address
bus without any qualification of the command sig-
nals. The STPC Atlas does not drive IOCS16#
(similar to PC-AT design). An ISA master access
to an internal register of the STPC Atlas is execut-
ed as an extended 8-bit IO cycle.
REF#
Refresh Cycle. This is the refresh command
signal of the ISA bus. It is driven as an output
when the STPC Atlas performs a refresh cycle on
the ISA bus. It is used as an input when an ISA
master owns the bus and is used to trigger a re-
fresh cycle.
The STPC Atlas performs a pseudo hidden re-
fresh. It requests the host bus for two host clocks
to drive the refresh address and capture it in exter-
nal buffers. The host bus is then relinquished
while the refresh cycle continues on the ISA bus.
AEN
Address Enable. Address Enable is enabled
when the DMA controller is the bus owner to indi-
cate that a DMA transfer will occur. The enabling
of the signal indicates to IO devices to ignore the
IOR#/IOW# signal during DMA transfers.
IOCHCK#
IO Channel Check. IO Channel Check
is enabled by any ISA device to signal an error
condition that can not be corrected. NMI signal be-
comes active upon seeing IOCHCK# active if the
corresponding bit in Port B is enabled.
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