參數(shù)資料
型號(hào)： STPCI2EEYC
廠商： STMICROELECTRONICS
元件分類： 外設(shè)及接口
英文描述： MULTIFUNCTION PERIPHERAL, PBGA516
封裝： PLASTIC, BGA-516
文件頁(yè)數(shù)： 60/80頁(yè)
文件大小： 854K
代理商： STPCI2EEYC
BOARD LAYOUT
63/80
Issue 0.4 - July 16, 2001
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
The maximum skew between pins for this part is
250ps. The important factors for the clock buffer
are a consistent drive strength and low skew be-
tween the outputs. The delay through the buffer is
not important so it does not have to be a zero de-
lay PLL type buffer. The trace lengths from the
clock driver to the DIMM CKn pins should be
matched exactly. Since the propagation speed
can vary between PCB layers, the clocks should
be routed in a consistent way. The routing to the
STPC memory input should be longer by 75mm to
compensate for the extra clock routing on the
DIMM. Also a 20 pF capacitor should be placed as
near as possible to the clock input of the STPC to
compensate for the DIMM’s higher clock load. The
impedance of the trace used for the clock routing
should be matched to the DIMM clock trace im-
pedance (60-75 ohms)
.To minimise crosstalk the
clocks should be routed with spacing to adjacent
tracks of at least twice the clock trace width. For
designs which use SDRAMs directly mounted on
the motherboard PCB all the clock trace lengths
should be matched exactly.
The DIMM sockets should be populated starting
with the furthest DIMM from the STPC device first
(DIMM1). There are two types of DIMM devices;
single row and dual row. The dual row devices re-
quire two chip select signals to select between the
two rows. A STPC device with four chip select
control lines could control either four single row
DIMMs or two dual row DIMMs.
When using DIMM modules, schematics have to
be done carefully in order to avoid data buses
completely crossed on the board. This has to be
checked at the library level. The DQM signals
must be exchanged using the same order.
Figure 5-13. Optimum Data Bus Layout for DIMM
DIM M
ST P C
S D R A M I/F
D[31:00]
D[64:32]
MD[31:00]
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STPCI2GDYIE 制造商:STMicroelectronics 功能描述:
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