參數(shù)資料
型號(hào)： STPCI2EEYC
廠商： STMICROELECTRONICS
元件分類： 外設(shè)及接口
英文描述： MULTIFUNCTION PERIPHERAL, PBGA516
封裝： PLASTIC, BGA-516
文件頁(yè)數(shù)： 20/80頁(yè)
文件大?。?/td> 854K
代理商： STPCI2EEYC
PIN DESCRIPTION
27/80
Issue 0.4 - July 16, 2001
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
BA[0]
Bank Address. Internal bank address line.
MD[63:0] Memory Data. This is the 64-bit memory
data bus. If only half of a bank is populated,
MD63-32 is pulled high, data is on MD31-0.
MD20-0 are also used as inputs at the rising edge
of PWGD to latch in power-up configuration infor-
mation into the ADPC strap registers.
RAS#[1:0]
Row Address Strobe. There are two
active-low row address strobe output signals. The
RAS# signals drive the memory devices directly
without any external buffering.
CAS#[1:0]
Column Address Strobe. There are
two active-low column address strobe output sig-
nals. The CAS# signals drive the memory devices
directly without any external buffering.
MWE#
Write Enable. Write enable specifies
whether the memory access is a read (MWE# = H)
or a write (MWE# = L). This single write enable
controls all DRAMs. The MWE# signals drive the
memory devices directly without any external buff-
ering.
3.3.3 PCI INTERFACE
AD[31:0]
PCI Address/Data. This is the 32-bit
multiplexed address and data bus of the PCI. This
bus is driven by the master during the address
phase and data phase of write transactions. It is
driven by the target during data phase of read
transactions.
PBE[3:0]# Bus Commands/Byte Enables. These
are the multiplexed command and Byte enable
signals of the PCI bus. During the address phase
they define the command and during the data
phase they carry the Byte enable information.
These pins are inputs when a PCI master other
than the STPC Atlas owns the bus and outputs
when the STPC Atlas owns the bus.
FRAME# Cycle Frame. This is the frame signal of
the PCI bus. It is an input when a PCI master owns
the bus and is an output when STPC Atlas owns
the PCI bus.
TRDY#
Target Ready. This is the target ready sig-
nal of the PCI bus. It is driven as an output when
the STPC Atlas is the target of the current bus
transaction. It is used as an input when STPC At-
las initiates a cycle on the PCI bus.
IRDY# Initiator Ready. This is the initiator ready
signal of the PCI bus. It is used as an output when
the STPC Atlas initiates a bus cycle on the PCI
bus. It is used as an input during the PCI cycles
targeted to the STPC Atlas to determine when the
current PCI master is ready to complete the cur-
rent transaction.
STOP# Stop Transaction. STOP# is used to im-
plement the disconnect, retry and abort protocol of
the PCI bus. It is used as an input for the bus cy-
cles initiated by the STPC Atlas and is used as an
output when a PCI master cycle is targeted to the
STPC Atlas.
DEVSEL# Device Select. This signal is used as
an input when the STPC Atlas initiates a bus cycle
on the PCI bus to determine if a PCI slave device
has decoded itself to be the target of the current
transaction. It is asserted as an output either when
the STPC Atlas is the target of the current PCI
transaction or when no other device asserts DEV-
SEL# prior to the subtractive decode phase of the
current PCI transaction.
PAR Parity Signal Transactions. This is the parity
signal of the PCI bus. This signal is used to guar-
antee even parity across AD[31:0], CBE[3:0]#,
and PAR. This signal is driven by the master dur-
ing the address phase and data phase of write
transactions. It is driven by the target during data
phase of read transactions. (Its assertion is identi-
cal to that of the AD bus delayed by one PCI clock
cycle)
PERR#
Parity Error
SERR# System Error. This is the system error sig-
nal of the PCI bus. It may, if enabled, be asserted
for one PCI clock cycle if target aborts a STPC At-
las initiated PCI transaction. Its assertion by either
the STPC Atlas or by another PCI bus agent will
trigger the assertion of NMI to the host CPU. This
is an open drain output.
LOCK#
PCI Lock. This is the lock signal of the PCI
bus and is used to implement the exclusive bus
operations when acting as a PCI target agent.
PCI_REQ#[2:0]
PCI Request. These pins are the
three external PCI master request pins. They indi-
cates to the PCI arbiter that the external agents
desire use of the bus.
PCI_GNT#[2:0]
PCI Grant. These pins indicate
that the PCI bus has been granted to the master
requesting it on its PCI_REQ#.
PCI_INT[3:0]
PCI Interrupt Request. These are
the PCI bus interrupt signals. They are to be en-
coded before connection to the STPC Atlas using
ISACLK and ISACLKX2 as the input selection
strobes.
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