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參數(shù)資料
| 型號： | STPCI2EEYC |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PBGA516 |
| 封裝： | PLASTIC, BGA-516 |
| 文件頁數(shù)： | 44/80頁 |
| 文件大?。?/td> | 854K |
| 代理商： | STPCI2EEYC |
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ELECTRICAL SPECIFICATIONS
49/80
Issue 0.4 - July 16, 2001
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
41c
I/O access to 16-bit ISA Slave
6T
Cycles
41d
I/O access to 8-bit ISA Slave
12T
Cycles
42
SA[19:0] SBHE valid to read data valid
42b
Memory access to 16-bit ISA Slave Standard cycle
4T
Cycles
42e
Memory access to 8-bit ISA Slave Standard cycle
10T
Cycles
42h
I/O access to 16-bit ISA Slave Standard cycle
4T
Cycles
42l
I/O access to 8-bit ISA Slave Standard cycle
10T
Cycles
47
MEMR#, MEMW#, SMEMR#, SMEMW#, IOR#, IOW # asserted to IOCHRDY negated
47a
Memory access to 16-bit ISA Slave
2T
Cycles
47b
Memory access to 8-bit ISA Slave
5T
Cycles
47c
I/O access to 16-bit ISA Slave
2T
Cycles
47d
I/O access to 8-bit ISA Slave
5T
Cycles
48
MEMR#, SMEMR#, IOR# asserted to read data valid
48b
Memory access to 16-bit ISA Slave Standard Cycle
2T
Cycles
48e
Memory access to 8-bit ISA Slave Standard Cycle
5T
Cycles
48h
I/O access to 16-bit ISA Slave Standard Cycle
2T
Cycles
48l
I/O access to 8-bit ISA Slave Standard Cycle
5T
Cycles
54
IOCHRDY asserted to read data valid
54a
Memory access to 16-bit ISA Slave
1T(R)/2T(W)
Cycles
54b
Memory access to 8-bit ISA Slave
1T(R)/2T(W)
Cycles
54c
I/O access to 16-bit ISA Slave
1T(R)/2T(W)
Cycles
54d
I/O access to 8-bit ISA Slave
1T(R)/2T(W)
Cycles
55a
IOCHRDY asserted to MEMR#, MEMW#, SMEMR#,
SMEMW#, IOR#, IOW# negated
1T
Cycles
55b
IOCHRY asserted to MEMR#, SMEMR# negated (refresh)
1T
Cycles
56
IOCHRDY asserted to next ALE# asserted
2T
Cycles
57
IOCHRDY asserted to SA[19:0], SBHE invalid
2T
Cycles
58
MEMR#, IOR#, SMEMR# negated to read data invalid
0T
Cycles
59
MEMR#, IOR#, SMEMR# negated to data bus float
0T
Cycles
61
Write data before MEMW# asserted
61a
Memory access to 16-bit ISA Slave
2T
Cycles
61b
Memory access to 8-bit ISA Slave (Byte copy at end of
start)
2T
Cycles
61
Write data before SMEMW# asserted
61c
Memory access to 16-bit ISA Slave
2T
Cycles
61d
Memory access to 8-bit ISA Slave
2T
Cycles
61
Write Data valid before IOW # asserted
61e
I/O access to 16-bit ISA Slave
2T
Cycles
61f
I/O access to 8-bit ISA Slave
2T
Cycles
64a
MEMW# negated to write data invalid - 16-bit
1T
Cycles
64b
MEMW# negated to write data invalid - 8-bit
1T
Cycles
64c
SMEMW# negated to write data invalid - 16-bit
1T
Cycles
64d
SMEMW# negated to write data invalid - 8-bit
1T
Cycles
64e
IOW # negated to write data invalid
1T
Cycles
Table 4-10. ISA Bus AC Timing
Name
Parameter
Min
Max
Units
Note: The signal numbering refers to Table 4-2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| STPCI2GDY | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:X86 Core PC Compatible System-on-Chip for Terminals |
| STPCI2GDYI | 功能描述:微處理器 - MPU 120MHz x86 SoC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| STPCI2GDYIE | 制造商:STMicroelectronics 功能描述: |
| STPCI2HDYC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PERIPHERAL (MULTIFUNCTION) CONTROLLER |
| STPCI2HEYC | 功能描述:微處理器 - MPU 133MHz x86 SoC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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