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| 型號： | STPCI2EEYC |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PBGA516 |
| 封裝： | PLASTIC, BGA-516 |
| 文件頁數(shù)： | 56/80頁 |
| 文件大?。?/td> | 854K |
| 代理商： | STPCI2EEYC |
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GENERAL DESCRIPTION
Issue 0.4 - July 16, 2001
6/80
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1 GENERAL DESCRIPTION
At the heart of the STPC Atlas is an advanced
processor block that includes a powerful x86 proc-
essor core along with a 64-bit SDRAM controller,
advanced 64-bit accelerated graphics and video
controller, a high speed PCI local-bus controller
and Industry standard PC chip set functions (Inter-
rupt controller, UltraDMA IDE Controller, Interval
timer and ISA bus).
The STPC Atlas has in addition, a TFT output, a
Video Input, a Local Bus interface, PCMCIA and
super I/O features including USB host hub.
The STPC Atlas makes use of a tightly coupled
Unified Memory Architecture (UMA), where the
same memory array is used for CPU main memo-
ry and graphics frame-buffer. This means a reduc-
tion in total system memory for system perform-
ances that are equal to that of a comparable frame
buffer and system memory based system, and
generally much better, due to the higher memory
bandwidth allowed by attaching the graphics en-
gine directly to the 64-bit processor host interface
running at the speed of the processor bus rather
than the traditional PCI bus.
The 64-bit wide memory array provides the sys-
tem with an 800MB/s peak bandwidth. This allows
for higher resolution screens and greater color
depth. The processor bus runs at 133 MHz, further
increasing “standard” bandwidth by at least a fac-
tor of two.
The ‘standard’ PC chipset functions (DMA, inter-
rupt controller, timers, power management logic)
are integrated together with the x86 processor
core; additional low bandwidth functions such as
communication ports are accessed by the STPC
Atlas via an internal ISA bus.
The PCI bus is the main data communication link
to the STPC Atlas chip. The STPC Atlas translates
appropriate host bus I/O and Memory cycles onto
the PCI bus. It also supports the generation of
Configuration cycles on the PCI bus. The STPC
Atlas, as a PCI bus agent (host bridge class), fully
complies with PCI specification 2.1. The chip-set
also implements the PCI mandatory header regis-
ters in Type 0 PCI configuration space for easy
porting of PCI aware system BIOS. The device
contains a PCI arbitration function for three exter-
nal PCI devices.
Graphics functions are controlled through the on-
chip SVGA controller and the monitor display is
produced through the 2D graphics display engine.
This Graphics Engine is tuned to work with the
host CPU to provide a balanced graphics system
with a low silicon area cost. It performs limited
graphics drawing operations which include hard-
ware acceleration of text, bitblts, transparent blts
and fills. The results of these operations change
the contents of the on-screen or off-screen frame
buffer areas of SDRAM memory. The frame buffer
can occupy a space up to 4 Mbytes anywhere in
the physical main memory.
The maximum graphics resolution supported is
1280 x 1024 in 16 Million colours at 75 Hz refresh
rate and is VGA and SVGA compatible. Horizontal
timing fields are VGA compatible while the vertical
fields are extended by one bit to accommodate
above display resolution.
To generate the TFT output, the STPC Atlas ex-
tracts the digital video stream before the RAM-
DAC and reformats it to the TFT format. The
height and width of the flat panel are programma-
ble through configuration registers up to a size of
1024 by 1024.
By default, lower resolution images cover only a
part of the larger TFT panel. The STPC Atlas al-
lows the user to expand the image vertically and
horizontally in text mode by inserting programma-
ble blank pixels. It allows expansion of the image
vertically and horizontally in graphics mode by
replicating pixels. The replication of J times every
K pixel is independently programmable in the ver-
tical and horizontal directions.
PanelLinkTM is a proprietary interconnect protocol
defined by Silicon Image, Inc. It consists of a
transmitter that takes parallel video/graphics data
from the host LCD graphics controller and trans-
mits it serially at high speed to the receiver which
controls the TFT panel. The TFT interface is de-
signed to support the connection of this control
signal to the PanelLinkTM transmitter.
The STPC Atlas PCMCIA controller has been spe-
cifically designed to provide the interface with PC-
Cards which contain additional memory or I/O and
provides an ExCATM implementation to PCMCIA
2.0 / JEIDA 4.1 standards.
The power management control facilities include
socket power control, insertion/removal capability,
power saving with Windows inactivity, NCS con-
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| STPCI2GDY | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:X86 Core PC Compatible System-on-Chip for Terminals |
| STPCI2GDYI | 功能描述:微處理器 - MPU 120MHz x86 SoC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| STPCI2GDYIE | 制造商:STMicroelectronics 功能描述: |
| STPCI2HDYC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PERIPHERAL (MULTIFUNCTION) CONTROLLER |
| STPCI2HEYC | 功能描述:微處理器 - MPU 133MHz x86 SoC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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