參數(shù)資料
型號(hào): SAA7381
廠商: NXP SEMICONDUCTORS
元件分類: 消費(fèi)家電
英文描述: ATAPI CD-R block decoder
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP144
文件頁數(shù): 7/108頁
文件大?。?/td> 380K
代理商: SAA7381
1997 Aug 12
7
Philips Semiconductors
Objective specification
ATAPI CD-R block decoder
SAA7381
n.c.
35 to 38
not connected
SDI1
39
I
C
I
2
S-bus I/O
data input from CD engine
n.c.
40
O
M
not connected
SFSY
41
I/O
L/C
subcode I/O
3-wire subcode sync input/output
RCK
42
I/O
L/C
3-wire subcode clock input/output
SUBI
43
I
C
Q and R-W subcode input
n.c.
44
O
L
not connected
CFLG
45
I
C
I
2
S-bus input
CD error corrector flags and absolute time
sync
CD C2 error correction flag input for ERCO
C2P0
46
I
C
DGND5
47
digital ground 5
IECO
48
O
M
multimedia
IEC 958 output
MCK
49
I/O
M/C
multimedia
output
256f
s
or 384f
s
clock for multimedia master
clock/IEC 958 clock or divided system clock for
CD-DSP
I
2
S-bus bit clock input/output
SCK2
50
I/O
L/C
multimedia
WS2
51
I/O
L/C
I
2
S-bus word select strobe input/output
SDO2
52
O
M
I
2
S-bus data output to DAC/video decoder
GND
53
ground
CROUT
54
O
crystal pad
crystal oscillator crystal oscillator output
CRIN
55
I
crystal pad
crystal oscillator/clock input
V
DDA
I
ref
POR
56
analog supply voltage
57
analog
current input
clock generator VCO reference current
58
I
Schmitt trigger
system
power-on reset (active LOW)
TEST1
59
I
C
test
mode control input test pins
TEST2
60
I
C
RESET
61
I
Schmitt trigger
host
ATAPI bus reset input from host (active LOW)
DD7
62
I/O
AL/T
host
data bus input/output
DD8
63
I/O
AL/T
DD6
64
I/O
AL/T
V
DDD(pad1)
DGND6
65
digital peripheral supply voltage 1
66
digital ground 6
DD9
67
I/O
AL/T
host
data bus pin order of ATAPI interface matches
the pinning of the 40-way IDE connector (slew
rate limiting by control of drive capability into
capacitive load of ATA bus)
DD5
68
I/O
AL/T
DD10
69
I/O
AL/T
DD4
70
I/O
AL/T
SYMBOL
PIN
TYPE
DRIVE/
THRESHOLD
GROUPING
DESCRIPTION
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