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參數(shù)資料
| 型號： | SAA7381 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | ATAPI CD-R block decoder |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP144 |
| 文件頁數(shù)： | 53/108頁 |
| 文件大小： | 380K |
| 代理商： | SAA7381 |
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1997 Aug 12
53
Philips Semiconductors
Objective specification
ATAPI CD-R block decoder
SAA7381
7.5.11
DMA
TRANSFERS IN GENERIC MODE
The host interface in generic mode will support two types
of DMA transfer to the NCR device, namely:
Normal DMA mode
Burst DMA mode.
Both of these modes are 8 bit DMA transfers. During data
transfers the microcontroller can suspend the DMA
transfer (via HICONF1 register ‘dmaen’ bit 7) under the
following conditions:
An Interrupt received
An abort received
A register read required.
7.5.12
N
ORMAL
DMA
MODE
In this mode the host Interface transfers data in single
bytes. This DMA mode is configured by setting ‘dmamode’
(DTCTR register bit 6) to zero, and DMA (DTCTR register
bit 5) to one. Data flow direction and byte counts are
configured the same as ATAPI DMA modes of data
transfer, but with command information being received via
the NCR SCSI controller registers external to the
SAA7381 operation. The data transfer takes place as long
as the DMA request signal DMARQ is true. The DMACK
signal is toggled by the host Interface for each byte
transferred as shown in Fig.5.
7.5.13
B
URST
DMA
MODE USING MULTIPLEXED BUS CONFIGURATION
In this mode the DMA data is available on the DMA bus when both, DBRD or DBWR and DMACK are true. DMACK
remains asserted throughout the transfer while DBRD toggles for each transfer as shown in Fig.6. To configure the host
interface the DMA mode and DMA bits (DTCTR bits 6 and 5) should be set to logic 1.
Fig.5 Generic interface normal DMA mode.
handbook, full pagewidth
MGK514
DMACK
DBRD/
DBWR
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