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參數(shù)資料
| 型號： | SAA7381 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | ATAPI CD-R block decoder |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP144 |
| 文件頁數(shù)： | 13/108頁 |
| 文件大小： | 380K |
| 代理商： | SAA7381 |
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1997 Aug 12
13
Philips Semiconductors
Objective specification
ATAPI CD-R block decoder
SAA7381
Table 4
ATAPI target mode interface
ATAPI
NAME
ATAPI MEANING
RESET
ATAPI reset signal: the SAA7381 will not recognize a signal assertion shorter than 20 ns as a valid
reset signal.
ATAPI D0 to D7.
DD8 to DD15 ATAPI D8 to D15: these data bits are only used in accesses to the 16-bit data port.
DMARQ
DMA request: this signal, used for DMA data transfers between host and device, is asserted by the
SAA7381 when it is ready to transfer data to or from the host. The direction of data transfer is
controlled by DIOR and DIOW.
DMACK
DMA acknowledge: this signal is used by the host in response to DMARQ to initiate DMA transfers.
This signal may be temporarily negated by the host to suspend the DMA transfer in process.
IOCS16
ATAPI I/O port is a 16-bit open-drain output: during PIO transfer Modes 0, 1 or 2, IOCS16 indicates to
the host system that the 16-bit data port has been addressed and that the device is prepared to send
or receive a 16-bit data word.
IORDY
ATAPI I/O ready open-drain output: this signal is negated to extend the host transfer cycle of any host
register access (read or write) when the SAA7381 is not ready to respond to a data transfer request.
This signal is only enabled during DIOR/DIOW cycles to the SAA7381. When IORDY is not active, it is
in the high-impedance (undriven) state.
DA0 to DA2
Address bus (device address).
DIOW
ATAPI write strobe: the rising edge of DIOW latches data from the signals, DD0 to DD7 or
DD0 to DD15 into a register or the data port of the SAA7381. The SAA7381 will not act on the data
until it is latched.
DIOR
ATAPI read strobe: the falling edge of DIOR enables data from a register or data port of the SAA7381
onto the signals, DD0 to DD7 or DD0 to DD15. The rising edge of DIOR latches data at the host and
the host will not act on the data until it is latched.
CS0
ATAPI chip select 0 input: this is the chip select signal from the host used to select the ATA command
block registers. This signal is also known as CS1FX.
CS1
ATAPI chip select 1 input: this is the chip select signal from the host used to select the ATA control
block registers. This signal is also known as CS3FX.
INTRQ
ATAPI interrupt output: this signal is used to interrupt the host system. INTRQ is asserted only when
the device has a pending interrupt, the device is selected, and the host has cleared the ‘nien’ bit in the
device control register. If the ‘nien’ bit is equal to 1, or the device is not selected, this output is in a
high-impedance state, regardless of the presence or absence of a pending interrupt.
PDIAG
ATAPI passed diagnostics: this signal shall be asserted by device 1 to indicate to device 0 that it has
completed diagnostics.
DASP
ATAPI DASP (device active, device 1 present): this is a time-multiplexed signal which indicates that a
device is active, or that device 1 is present. This signal is an open-drain output.
DD0 to DD7
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