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參數(shù)資料
| 型號： | SAA7381 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | ATAPI CD-R block decoder |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP144 |
| 文件頁數(shù)： | 32/108頁 |
| 文件大小： | 380K |
| 代理商： | SAA7381 |
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1997 Aug 12
32
Philips Semiconductors
Objective specification
ATAPI CD-R block decoder
SAA7381
7.4
Interrupt registers
The interrupt system in the SAA7381 is intended to make it possible to acknowledge interrupts both independently
without interference or together. There are two interrupt pins to the sub-CPU from the SAA7381. The INT pin is
associated only with the host interface register IFSTAT (address FF92H). The INT2 pin is associated with 6 interrupt
registers which cover the SAA7381 drive block and UART. Two status/reset registers and two interrupt enable register
for the drive block and one status/reset register plus an interrupt enable register for the UART.
Table 44
IFSTAT interrupt register for the host interface; address FF92H (note 1)
Note
1.
Interrupt status bits are described in the host interface; see Section 7.5.3.18.
7.4.1
I
NTERRUPT
1
By writing a logic 1 to the INT1RESET register the bits will negate the INT1STATUS register bits. Writing a logic 1 to an
INT1ENABLE bit will enable the corresponding status bit. Writing a logic 0 will disable the status to zero.
Table 45
INT1STATUS: drive interrupt register status; address FF7AH (see Table 54)
Table 46
INT1RESET: drive interrupt register reset; address FF7AH (see Table 54)
7.4.1.1
INT1ENABLE: drive interrupt register enable bits
Table 47
INT1ENABLE: drive interrupt register enable; address FF7BH (see Table 54)
ACCESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
R
cmdi
dtei
drqi
ultra_stop
dtbsy
srsti
reset08
a0comp/
crc_error
ACCESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
R
dec
nocor
erablk
cblk
uceblk
crc-ng
q-ng
int2
ACCESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
W
dec
nocor
erablk
cblk
uceblk
crc-ng
q-ng
ACCESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
W
dec
nocor
erablk
cblk
uceblk
crc-ng
q-ng
int2
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