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參數(shù)資料
| 型號： | SAA7381 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | ATAPI CD-R block decoder |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP144 |
| 文件頁數(shù)： | 14/108頁 |
| 文件大小： | 380K |
| 代理商： | SAA7381 |
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1997 Aug 12
14
Philips Semiconductors
Objective specification
ATAPI CD-R block decoder
SAA7381
Table 5
Generic host controller interface
Table 6
Miscellaneous pins
Table 7
Sub-CPU interface pins
ATAPI
NAME
GENERIC
INTERFACE
NAME
GENERIC HOST CONTROLLER INTERFACE MEANING
RESET
DD0 to DD7
DD8 to DD15 D8 to D15
DMARQ
DMACK
DA1
DA2
CS0
RESET
D0 to D7
controller reset output
controller DMA path/controller data and control bus (optional)
controller upper DMA path (optional)
DMA acknowledge to controller
DMA request from controller
DMA bus write to controller
DMA bus read from controller
controller chip select output for sub-CPU read/write cycles
DMACK
DMARQ
DBWR
DBRD
SCSICS
SYMBOL
DESCRIPTION
COMMENT
CRIN
CROUT
I
ref
POR
TEST1 and TEST2
crystal oscillator/clock input
crystal oscillator output
VCO reference current
power-on reset pin
mode control test pins
clock PLL multiplier
SYMBOL
DESCRIPTION
COMMENT
SRST
sub-CPU reset
active HIGH reset if XDD7 is pulled LOW during power-on reset;
active LOW reset if XDD7 is pulled HIGH during power-on reset
open-drain sub-processor interrupt from host interface
INT
sub-CPU interrupt request
output from host interface
sub-CPU interrupt output
from the SAA7381 drive
block and UART
sub-CPU clock out
sub-CPU read enable
INT2
open-drain sub-processor interrupt from drive and UART
SCCLK
RD
sub-CPU read enable strobe; if grounded permanently, the WR
signal will act as read/write control input
write enable; alternative usage is read/write if RD is held LOW at all
times; WR has priority over RD at all times
while HIGH, the lower address bits are latched from
SCD0 to SCD7; should be used with a Schmitt trigger input to
avoid false latching due to ground bounce on the
8051 microcontroller
this pin should be tied high using a 10 k
resistor
WR/R/W
sub-CPU write enable/
read/write control
demultiplex enable input for
lower address lines
ALE
PSEN
SCD0 to SCD7/
SCA0 to SCA7
SCA8 to SCA15
program store enable
sub-CPU data bus
multiplexed/low address bus
sub-CPU address high bits
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