參數(shù)資料
型號(hào)： SAA7381
廠(chǎng)商： NXP SEMICONDUCTORS
元件分類(lèi)： 消費(fèi)家電
英文描述： ATAPI CD-R block decoder
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP144
文件頁(yè)數(shù)： 29/108頁(yè)
文件大小： 380K
代理商： SAA7381
1997 Aug 12
29
Philips Semiconductors
Objective specification
ATAPI CD-R block decoder
SAA7381
7.3.4
IEC 958/EBU
OUTPUT
Table 39
Description of the IECCTRL register control bits (notes 1 and 2)
Notes
1.
2.
In order for the IEC interface to operate correctly, it will require a clock at 128f
s
to be present.
The ‘vbit’ is copied into the V bit of the IEC 958 frame.
Table 40
IEC 958 system channel bit mapping (note 1)
Note
1.
The C bit is updated on an IEC frame-by-frame basis, the bit offset corresponds to the IEC frame offset. They are
repeated for both left and right channels. Bit 0 is present in the C bit of the first sample pair of the IEC superframe of
192 sample pairs.
BIT
NAME
VALUE
DESCRIPTION
7
iecen
0
1
0
1
0
1
0
1
IEC 958 interface is off
IEC 958 Interface is on
IEC 958 contains audio information
IEC 958 contains data
IEC 958 C bit in system channel is logic 0
IEC 958 C bit in system channel is logic 1
audio pre-emphasis off/IEC 958 contains data
audio pre-emphasis on (only appears in IEC 958 C channel;
de-emphasis bit is not implemented in the SAA7381)
audio samples suitable for conversion
mute audio, or signal is data and should not be digital-to-analog
converted at any time
reserved
reserved
level II clock accuracy
level III clock accuracy (depends on mck/system clock)
reserved
reserved
6
data
5
copyright
4
preem
3
vbit
0
1
2
1 to 0
accu
00
01
10
11
BIT NUMBER
BIT OFFSET
+0
+1
+2
+3
+4
cat4
0
accu0
+5
+6
+7
0
8
16
24
0
data
cat1
0
0
copyright
cat2
0
0
preem
cat3
0
0
0
0
0
cat0
0
0
cat5
0
accu1
cat6
0
0
cat7
0
0
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