參數(shù)資料
型號： SAA7381
廠商： NXP SEMICONDUCTORS
元件分類： 消費家電
英文描述： ATAPI CD-R block decoder
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP144
文件頁數(shù)： 39/108頁
文件大小： 380K
代理商： SAA7381
1997 Aug 12
39
Philips Semiconductors
Objective specification
ATAPI CD-R block decoder
SAA7381
7.5.3.6
RESET
Writing to this register resets the SAA7381 and initializes all the registers on the device.
Table 59
RESET; address FF86H (note 1)
Note
1.
The ‘hsel’ bits (see Table 60) control the mode of operation of the host interface block. After a power-on reset the
‘hsel’ bits default to 000, i.e. the host 3-state pins are 3-stated. The firmware must configure the ‘hsel’ bits for the
desired mode of operation after every hardware reset. It should be noted that any write operation by the
microcontroller to this register will result in the resetting of all other SAA7381 registers to their default condition.
Table 60
Description of the ‘hsel’ bits
7.5.3.7
ASTAT
This is the ATAPI status register.
Table 61
ASTAT: address FF87H (notes 1 and 2)
Notes
1.
The ‘bsy’ flag bit 7 will be set to logic 1 when:
a) The host writes to the ACMD register and the SAA7381 is the selected drive.
b) The host writes the execute drive diagnostic command (90H) to the ACMD register.
c) The host writes to the ADCTR register and sets the ‘srst’ bit.
d) There is a hardware reset.
If a host interrupt is asserted then it will be cleared by writing to this register.
2.
7.5.3.8
ITRG
In the ATAPI mode writing to this register generates a PC host interrupt on the INT pin. This interrupt is cleared when
the PC host reads the ATAPI status register (ASTAT) or writes to the ATAPI command register.
7.5.3.9
ADRADR
This is the ATAPI drive address register for the SAA7381. This uses an obsolete register address (CS1
→
DA0 = 10111)
from the ATAPI register map in the ATAPI specification. Bit 7 of this register is high-impedance when read by the host.
After a reset the ATAPI registers are all cleared except for the ASTAT register which has its ‘bsy’ bit set.
ACCESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
W
reserved
hsel
hsel2 to hsel0
HOST INTERFACE MODE
DESCRIPTION
000
001
011
100
others
unknown host
ATAPI
generic 8-bit
generic 16-bit
reserved
all host pins 3-state, default after hardware reset
ATAPI Interface mode
generic interface mode, with 8-bit transfers
generic interface mode, with 16-bit transfers
for future enhancements
ACCESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RW
bsy
drdy
dmar
dsc
drq
corr
reset
check
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