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參數(shù)資料
| 型號： | SAA7381 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | ATAPI CD-R block decoder |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP144 |
| 文件頁數(shù)： | 18/108頁 |
| 文件大小： | 380K |
| 代理商： | SAA7381 |
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1997 Aug 12
18
Philips Semiconductors
Objective specification
ATAPI CD-R block decoder
SAA7381
7.2
CD input control registers
The CD input process is intended to be as automated as possible. Data is read in from the front end, descrambled if in
CD-ROM mode and then written to RAM. The registers that control the address of where the data is written to are in the
memory processor block.
The input data is synchronized, decoded and written to the buffer RAM. The input data format is software programmable.
The synchronization is performed by using a sync detector and a sync interpolator. The sync detector can detect
CD-ROM syncs and syncs from the CFLG pin, for use with Red Book, audio and for DVD. When no sync is found, it is
optionally interpolated.
After decoding, each full sector of data (2352 bytes) comprising sync, header and sub-header is written to the buffer
RAM. The R-W and Q subcode is added by a software-initiated automatic block copy process.
7.2.1
R
EGISTERS ASSOCIATED WITH DATA IN PROCESS
Table 12
IFCONFIG (write only; address FF10H) (see Table 13)
Table 13
Description of the IFCONFIG register bits
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ipconfig
ckdiv1
ckdiv0
subsel
modulo 1
modulo 0
config swap
config wclk
BIT
NAME
VALUE
MEANING
7
ipconfig
0
1
00
01
10
11
0
1
00
01
10
11
0
1
0
1
I
2
S-bus mode
EIAJ serial interface mode
oversample, bit clock division ratio = 2
oversample, bit clock division ratio = 4
oversample, bit clock division ratio = 8
bit clock division ratio = 1 (no division)
both copies of sub-header contribute to STAT1/sh0err to sh3err
first copy only of sub-header contributes to STAT1/sh0err to sh3err
modulo count 2352
6 and 5
ckdiv1 and
ckdiv0
4
subsel
3 and 2
modulo 1 and
modulo 0
modulo count 2064
modulo count 2064, but do not count bytes with flag = 1
the received data from the CD-DSP or drive FIFO is not swapped
the received data from the CD-DSP or drive FIFO is swapped
the internal ‘irclk’ is not inverted
the internal ‘irclk’ is inverted
1
config swap
0
config wclk
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