參數(shù)資料
型號： SAA7381
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： ATAPI CD-R block decoder
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP144
文件頁數(shù)： 59/108頁
文件大?。?/td> 380K
代理商： SAA7381
1997 Aug 12
59
Philips Semiconductors
Objective specification
ATAPI CD-R block decoder
SAA7381
7.7.3
S
UBPAGE
The lowest 52 kbytes (0X000H to 0XCFFFH) of the external data memory is mapped to SUBPAGE1. If the user requires
less RAM than is provided here (up to 52 kbytes), the 1024 byte granularity of positioning the offsets permits the pages
to be overlapped. In the fast RAM access mode, the lowest 48 kbytes are not accessible as they are assumed to be ROM
space.
The next 4 kbytes (0XD000H to 0XDFFFH) of the external data memory is always mapped to SUBPAGE2, and is always
available.
Table 89
Subpage RAM offsets
7.7.3.1
Sub-CPU segment page
The sub-CPU may access three adjacent segments of data offset from the base segment pointed to by ‘subseg’. These
are mapped as a contiguous 7.5 kbytes block at the top of memory from 0XE000 to 0XF800.
The buffer address is formed using the following equation:
Buffer address
subseg down to 0
=
This permits the writing of headers and looking at subcode information which may span more than one segment. Linked
lists in the ‘spare’ space at the end of a segment may be more easily manipulated if the segment and its neighbours are
visible to the sub-CPU in a consistent manner.
It is also possible to indirectly access any part of RAM by using the block copy registers to move the data to and from
the sub-CPU subpages.
7.7.3.2
Sub-CPU segment page restriction
It should be noted that the SAA7381 device does not have the concept of a defined upper limit on the segment addressed
block. Hence the segment page is always 3 contiguous segments of RAM, even when near or at the top of accessible
RAM or at the top of the firmware defined data input buffer. In this case 1 or 2 of the blocks accessed will be beyond the
buffer.
Table 90
Sub-CPU segment RAM offsets
7.8
External memory interface
The external memory interface is designed to operate with up to 128 Mbits hyper-page 33 MHz DRAM (EDO RAM) It is
also designed to operate with fast-page DRAM giving a 17.5 Mbyte/s burst transfer rate. Figures 13 and 14 illustrate the
timing diagram for fast-page mode.
It should be noted that during the power-on reset cycle it is necessary to pull the XDATA bus to all zeros to configure the
SAA7381 for use with the 8051 microcontroller.
ADDRESS
NAME
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FF18H
FF19H
FF1AH
FF1BH
SUBPAGE1-H
SUBPAGE1-L
SUBPAGE2-H
SUBPAGE2-L
a23
a15
a23
a15
a22
a14
a22
a14
a21
a13
a21
a13
a20
a12
a20
a12
a19
a11
a19
a18
a10
a18
a10
a17
a17
a16
a16
ADDRESS
NAME
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FF1CH
FF1DH
SUBSEG-H
SUBSEG-L
s7
s6
s5
s4
s3
s11
s2
s10
s1
s9
s0
s8
)
2560
sub-CPU (a12 down to 0)
+
×
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