
1997 Aug 12
15
Philips Semiconductors
Objective specification
ATAPI CD-R block decoder
SAA7381
Table 8
RAM interface pins
Table 9
Basic engine interface
SYMBOL
DESCRIPTION
COMMENT
XDA0 to XDA11
XRAS
XCAS
XWR
XDD0 to XDD7
RAM address bits, multiplexed for DRAM
DRAM row address strobe
DRAM column address strobe
RAM write enable
RAM data bus
up to 16 Mbytes DRAM only supported
SYMBOL
DESCRIPTION
COMMENT
SYSSYNC
COMSYNC
COMIN
COMOUT
COMCLK
COMACK
basic engine synchronization input
basic engine synchronization input
receive data
transmit data
serial data clock for synchronous mode
command acknowledge/transmit flow
control
generate interrupts on rising and/or falling edges
generate interrupts on rising and/or falling edges
must be HIGH for synchronous mode to transmit next
data byte
7
FUNCTIONAL DESCRIPTION
The SAA7381 device consists of a number of main
functional units; a CD engine interface, a multimedia block,
a microcontroller interface, an error detection and
correction block, a host interface and a memory manager.
There are also several smaller blocks including a clock
control block and a UART for communication with the CD
engine. Each block is independently controlled by a
dedicated register set. These registers are memory
mapped to the sub-CPU to allow for faster access.
The external RAM can also be accessed directly from the
microcontroller to support scratchpad accesses and thus
eliminate the need for further memory devices in the
system.
7.1
Memory field description
The CD input function of the SAA7381 buffer manager
receives the main data stream in I
2
S-bus format from the
CD-DSP, performs sync detection and partitions the data
into blocks.
It then writes the blocks to the buffer memory and onboard
ERCO RAM. Any detected errors are then corrected and
over written into the buffer memory.
Memory is segmented and addressable by segment
pointers. The segment pointers consist of a block number,
offset pointer and byte number within the block. The data
within each segment is organised in the same manner
(see Table 10).
The arrangement of data within each segment in memory
differs from other Philips devices, because of the different
error correction processing possibilities within the
SAA7381.
Addresses 0 to 2355 are written to memory by the drive
processor when enabled.