參數(shù)資料
型號(hào)： SAA7381
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： ATAPI CD-R block decoder
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP144
文件頁數(shù)： 48/108頁
文件大?。?/td> 380K
代理商： SAA7381
1997 Aug 12
48
Philips Semiconductors
Objective specification
ATAPI CD-R block decoder
SAA7381
Table 81
Description of the HIDEV register bits
BIT
7
NAME
pdiag out
DESCRIPTION
this bit is the passed diagnostics signal output from the SAA7381
pdiag out = 1; writing logic 1 to this bit drives the PDIAG pin HIGH if the pad enable
(‘pdiag enable’ bit 6) is set to logic 1. It is recommended that this bit is written LOW and
that the enable bit is driven to emulate an open-collector output.
pdiag out = 0; writing logic 0 to this bit sets the PDIAG pin LOW if the pad enable
(‘pdiag enable’ bit 6) is set to logic 1
this bit default is an input to the SAA7381
pdiag pad enable = 1; writing logic 1 to this bit enables the PDIAG driver output of the
SAA7381
pdiag pad enable = 0; default on power-up allowing external control of the ‘pdiag in’ bit 3
This bit is the device active slave present signal output. This pin is open-collector with an
external pull-up resistor. The DASP bit must be set to logic 1 in order to determine if any
other device is driving this signal.
dasp out = 1; writing logic 1 to this bit drives DASP HIGH if the pad enable (‘dasp enable’
bit 4) is set to logic 1. It is recommended that this bit is written LOW and that the enable
bit is driven to emulate an open-collector output.
dasp out = 0; writing logic 0 to this bit sets the DASP pin LOW if the pad enable (dasp
enable bit 4) is set to logic 1
this bit default is an input to the SAA7381
dasp pad enable = 1; writing logic 1 to this bit enables the DASP driver output of the
SAA7381
dasp pad enable = 0; default on power-up allowing external control of the dasp in bit 2
this bit is the passed diagnostics signal input to the SAA7381, only valid if ‘pdiag enable’
bit 6 is set to logic 0 (default = 0)
this bit is the device active slave present signal input to the SAA7381, only valid if
‘dasp enable’ bit 4 is set to logic 0 (default = 0)
This bit allows the host interface to increase its priority rating when requesting a data
transfer between itself and the SAA7381 memory processor. With host high priority set the
host data transfer requests are given the second highest priority, the highest given to the
microcontroller.
hosthipi = 1; writing logic 1 increase host interface priority above all other data transfer
requests, bar the microcontroller.
hosthipi = 0; writing logic 0 to this bit (default setting) gives low priority to the host
interface data transfer request.
6
pdiag pad
enable
5
dasp out
4
dasp pad
enable
3
pdiag in
2
dasp in
0
hosthipi
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