參數(shù)資料
型號(hào)： SAA7381
廠(chǎng)商： NXP SEMICONDUCTORS
元件分類(lèi)： 消費(fèi)家電
英文描述： ATAPI CD-R block decoder
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP144
文件頁(yè)數(shù)： 45/108頁(yè)
文件大?。?/td> 380K
代理商： SAA7381
1997 Aug 12
45
Philips Semiconductors
Objective specification
ATAPI CD-R block decoder
SAA7381
Table 75
Description of the HICONF1 register bits
BIT
NAME
DESCRIPTION
7
dmaen
DMA suspend: this bit controls whether DMA transfers in generic mode are suspended
dmaen = 1; host Interface DMA data transfers in generic can be temporarily interrupted
dmaen = 0; host Interface DMA data transfers in generic mode cannot be suspended
this bit allows statistical host high priority to be turned off
shhpbit = 0; (default) statistical host high priority turned on
shhpbit = 1; statistical host high priority turned off
this bit allows ‘udma’ to be turned off at the end of a transfer
udmaoff = 0; (default) switch off the ‘ultra_ata’ bit in the DTCTR register
udmaoff = 1; do nothing
Flush 12-byte command FIFO: writing a logic 1 to this bit will ‘flush’ clear the command
FIFO pointer to zero. Clearing the pointer is required if a spurious command is received
while the FIFO is being loaded and is also used to ensure a 12-byte command read by the
auto sequencer.
flushfifo = 1; writing a logic 1 clears the FIFO pointer to zero
flushfifo = 0; do nothing
Unmask data transfer end interrupt during ‘a(chǎn)utodrq’ sequence: this bit will disable the auto
sequencer masking of the ‘dtei’ interrupts during the ‘a(chǎn)utodrq’ sequence. The ‘dtei’, bit 6 of
the IFSTAT register is not effected by ‘unmaskdtei’. If ‘unmaskdtei’ is asserted the
sequencer on detecting the next ‘dtei’ interrupt, will set the ‘bsy’ flag, negate the ‘drq’ flag
and suspend operation. The microcontroller may then reconfigure the host interface
before negating unmaskdtei bit. When ‘unmaskdtei’ is negated the sequencer will negate
the ‘dtei’ interrupt and operate as normal.
unmaskdtei = 1; disable ‘a(chǎn)utodrq’ sequencer masking of ‘dtei’ interrupts and suspend the
sequence operation on next ‘dtei’ interrupt
unmaskdtei = 0; no effect, or restart ‘a(chǎn)utodrq’ sequencer operation
Clear auto sequencer transfer counter and packet size store to zero: this bit will clear the
transfer counter and packet size store to zero if a logic 1 is written to it. After the write
operation the registers operate as normal and the ‘clear_reg’ bit will have no effect unless
written to again.
clear_reg = 1; clears to zero transfer counter and packet size store
clear_reg = 0; no effect
ultra control bit 3; see Section 7.5.3.22
6
shhpbit
5
udmaoff
4
flushfifo
2
unmaskdtei
1
clear_reg
0
ultractrl3
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