參數(shù)資料
型號： SAA7381
廠商： NXP SEMICONDUCTORS
元件分類： 消費家電
英文描述： ATAPI CD-R block decoder
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP144
文件頁數(shù)： 56/108頁
文件大?。?/td> 380K
代理商： SAA7381
1997 Aug 12
56
Philips Semiconductors
Objective specification
ATAPI CD-R block decoder
SAA7381
7.7
8051 CPU and memory management functions
The 8051 CPU and memory management functions are as
follows:
Device registers are memory mapped for faster direct
access to the chip
Provides direct access from sub-CPU to buffer RAM to
support scratchpad accesses; this eliminates the need
for extra RAM chips in the system
Address space reserved for generic host interface
control and status pass-through (it is shared with ATAPI
register space; see Section 7.5)
Interfaces to 8051 multiplexed address and data bus
Two dynamically controllable RAM access modes allow
trade-off between accessible scratchpad RAM size and
RAM access time.
7.7.1
S
UB
-CPU
BUS ACCESS TIMING
The fast and slow RAM access timing diagrams are
illustrated in Figs 10 and 9. It should be noted that fast
RAM access is not recommended due to its negative effect
on the RAM bandwidth and the overall system
performance.
In the fast RAM access mode all external accesses below
C000 are expected to be program fetches. A DRAM
access cycle is not begun. Above C000, the RAM cycle
begins on the falling edge of ALE hence the number of
8051 wait states can be reduced. This is not however
recommended.
The disadvantage is, that the RAM access cycle is started
regardless of whether it will be needed. This has the effect
of aborting any other on-going use of the buffer memory
and reducing the available bandwidth.
Consequently, the number of wait states on accessing
RAM must be greater. In return, more RAM is accessible.
In the slow RAM access mode the RAM access cycle
starts on the falling edge of RD or WR, if PSEN is HIGH,
this being the first time in the 8051 external memory
access cycle that it is possible to determine that an XDATA
access is in fact being made.
This access mode has a lower impact on the buffer RAM
memory bandwidth as only accesses that are needed are
made. The two modes are under control of a register bit,
and it is possible to switch between them at any time.
Fig.9 Slow RAM access mode timing.
handbook, full pagewidth
MGK516
(3)
(1)
(2)
(4)
sub-CPU clock
sub-CPU ALE
XDA8
to
XDA15
XDA0 to XDA7, XDA8 to XDA15 latched
XDD0 to XDD7
RD/WR
(1) SAA7381 accesses RAM and stops clock until complete.
(2) RD LOW or WR LOW indicates access actually taking place.
(3) 8051 microcontroller continues.
(4) Address decoded for possible access RAM.
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