參數(shù)資料
型號： SAA7381
廠商： NXP SEMICONDUCTORS
元件分類： 消費家電
英文描述： ATAPI CD-R block decoder
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP144
文件頁數(shù)： 33/108頁
文件大?。?/td> 380K
代理商： SAA7381
1997 Aug 12
33
Philips Semiconductors
Objective specification
ATAPI CD-R block decoder
SAA7381
7.4.2
I
NTERRUPT
2
By writing a logic 1 to INT2RESET register bits will negate the INT2STATUS bit. Writing a logic 1 to an INT2ENABLE bit
will enable the corresponding status bit. Writing a logic 0 will disable the status to zero.
Table 48
INT2STATUS: drive interrupt register status; address FF7CH (see Table 54)
Table 49
INT2RESET: drive interrupt register reset; address FF7CH (see Table 54)
Table 50
INT2ENABLE: drive interrupt register enable; address FF7DH (see Table 54)
7.4.3
UART
INTERRUPT
By writing a logic 1 to the INT2RESET register bits will negate the INT2STATUS bit. Writing a logic 1 to an INT2ENABLE
bit will enable the corresponding status bit. Writing a logic 0 will disable the status to zero.
The INT2 interrupt corresponds to not (INT1 or INT2 or UARTINT).
Table 51
UARTINTSTATUS: UART interrupt register status; address FF78H (see Table 54)
Table 52
UARTINTRESET: UART interrupt register reset; address FF78H (see Table 54)
Table 53
UARTINTENABLE: UART interrupt register enable; address FF79H (see Table 54)
ACCESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
R
hostbyte
countzero
drive
reload
hostrel
countzero
copyend
subcode
syncint
dmatxint
int1
uartint
ACCESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
W
hostbyte
countzero
drive
reload
hostrel
countzero
copyend
subcode
syncint
dmatxini
ACCESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
W
hostbyte
countzero
drive
reload
hostrel
countzero
copyend
subcode
syncint
dmatxini
ACCESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
R
comsync
syssync
notcomsync
notsyssync
nottxbfull
rxbfull
overrun
rxparity
ACCESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
W
comsync
syssync
notcomsync
notsyssync
nottxbfull
rxbfull
overrun
rxparity
ACCESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
W
comsync
syssync
notcomsync
notsyssync
nottxbfull
rxbfull
overrun
rxparity
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