參數(shù)資料
型號(hào)： SAA7381
廠(chǎng)商： NXP SEMICONDUCTORS
元件分類(lèi)： 消費(fèi)家電
英文描述： ATAPI CD-R block decoder
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP144
文件頁(yè)數(shù)： 60/108頁(yè)
文件大?。?/td> 380K
代理商： SAA7381
1997 Aug 12
60
Philips Semiconductors
Objective specification
ATAPI CD-R block decoder
SAA7381
7.8.1
DRAM
INTERFACE CONFIGURATION REGISTER
Table 91
DRAM_CONFIG: address FF6AH (see Table 92)
Table 92
Description of the DRAM interface features
ACCESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
W
feature 4
feature 3
feature 2
feature 1
feature 0
feature 4
feature 3
feature 2
feature 1
feature 0
OPTION
0
1
X
X
X
X
X
X
X
1
0
X
X
X
X
X
X
X
1
1
0
X
X
X
X
0
1
X
X
X
X
X
X
X
X
refresh every 256 system clock cycles
refresh every 511 system clock cycles
minimum RAS LOW is 2 clock cycles
minimum RAS LOW is 3 clock cycles
1 Mbit
×
4 DRAM used
4 Mbit
×
4 DRAM used
512 kbits
×
8, 1 Mbit
×
8, 2 Mbits
×
8, 4 Mbits
×
8,
8 Mbits
×
8 or 16 Mbits
×
8 DRAM used
use fast-page mode device
use hyper-page mode device
X
X
X
X
X
X
X
X
0
1
7.9
UART for communication with CD engine
The following are required for communication with the CD
engine:
Clock prescaler for selectable baud rate
Synchronous slave peripheral interface
Asynchronous UART
DMA to reduce sub-CPU loading in SPI mode
Interrupt options available.
7.9.1
UART
BASIC ENGINE INTERFACE
The basic engine interface implements both a
synchronous peripheral interface and an asynchronous
high-speed serial interface. The same registers are shared
between the functions involved. Transmitted and received
data in asynchronous mode is sent or received with parity
bits in 8-bit, one parity bit, one STOP bit format.
The registers that are implemented are described below.
Two 16-bit DMA pointers (SPI_RX_OFF and
SPI_TX_OFF) are provided so that the interface may be
used in a DMA mode. As a byte is transferred to or from
the UART registers, it is possible to copy it into a part of the
AUXSEG RAM (16-bit register AUXSEGMENT-H or
AUXSEGMENT-L) in the SAA7381s buffer memory.
The pointers auto-increment and wrap within the region
assigned, so if the user wishes the data to appear in the
same place in the buffer for each DMA transfer it will be
necessary to reload these pointers before re-enabling
DMA for the data transfer.
DMA operation can be independently on for the transmit
and receive channels.
To enable the DMA receive channel the
UART_DMA_CTRL bit 7 must be set to logic 1. When the
receive DMA channel is active the sub-CPU cannot read
the receive register (RXDATA address FF77H) any more
but the SAA7381 will automatically copy the contents of
the RXDATA register to the address pointed at by the
SPI_RX_OFFSET pointer if it is full, increment the
SPI_RX_OFFSET pointer and reset the ‘rvbfull’ bit.
The SPI offset registers are available in both synchronous
and asynchronous modes and not just for SPI.
The SPI_RX_OFFSET register may be read to determine
how many bytes have been received.
The polarity of the SPI clock is selectable from the
UARTCOM register (see Table 94).
To enable the DMA transmit channel the
UART_DMA_CTRL bit 6 must be set to logic 1 and, at the
same time, bits 5 to 0 (‘txdmacount’) must be greater than
zero. When the transmit channel is active the sub-CPU
can write to the transmit register (TXDATA
address FF77H), however, the SAA7381 will automatically
perform the following operation.
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