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參數(shù)資料
| 型號： | SAA7381 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | ATAPI CD-R block decoder |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP144 |
| 文件頁數(shù)： | 19/108頁 |
| 文件大?。?/td> | 380K |
| 代理商： | SAA7381 |
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1997 Aug 12
19
Philips Semiconductors
Objective specification
ATAPI CD-R block decoder
SAA7381
Table 14
CD input control registers (see Table 15)
There are two sets of address registers, one giving the current (DRIVECURSEG) number of the segment being filled and
a segment/block counter. The other set contains the values (DRIVENEXTSEG) to use on completion of the current group
of blocks being filled or emptied (in CD-R). The DRIVEPREVSEG register is loaded with the value of the DRIVECURSEG
register at the end of each CD-ROM block.
The reloading of the registers will trigger an interrupt, if enabled, of the sub-CPU, which will then have to reload the ‘next’
registers. before the transfer requested in the ‘current’ registers are exhausted.
Memory is split into segments, each segment is 2560 bytes. The drive data is written one block at a time at the segment
number pointed to by the DRIVECURSEG register. For the next block the ‘DRIVECURSEG’ is updated as follows.
Table 15
Description of the ‘incen’ and ‘wren’ bits (see Table 14)
Notes
1.
If ‘incen’ is logic 1, the ‘DRIVECURSEG’ pointer will increment every sector sync. The ‘DRIVECURCOUNT’ will
decrement every sector sync independent of ‘incen’. If ‘incen’ is logic 0 then the pointer will remain fixed pointing at
the same segment of RAM. If the reading of data from CD is enabled by the ‘wrreq’ bit in the CTRL0 register, and
the ‘wren’ bit is logic 0 the segment will be repeatedly filled by the data coming in from the CD-ROM.
If ‘wren’ is logic 1 and ‘incen’ is logic 1 then the DRIVECURSEG register will increment with each sync time and the
DRIVECURCOUNT register will decrement but data will not be written to external RAM. This allows the triggering of
the reading of data or the writing of data some time in the future.
2.
Table 16
Control and status registers (see Tables 17, 18 and 19)
ADDRESS
NAME
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FF21H
FF20H
FF60H
FF27H
FF26H
FF61H
FF23H
FF22H
FF24H
FF25H
DRIVECURSEG-L
DRIVECURSEG-H
DRIVECURCOUNT
DRIVENEXTSEG-L
DRIVENEXTSEG-H
DRIVENEXTCOUNT
DRIVEPREVSEG-L
DRIVEPREVSEG-H
DRIVEOFFSET-H
DRIVEOFFSET-L
s7
s6
s5
c5
s5
c5
s5
s5
s5
s4
s12
c4
s4
s12
c4
s4
s12
s4
s4
s3
s11
c3
s3
s11
c3
s3
s11
s3
s3
s2
s10
c2
s2
s10
c2
s2
s10
s2
s2
s1
s9
c1
s1
s9
c1
s1
s9
s1
s1
s0
s8
c0
s0
s8
c0
s0
s8
s0
s0
incen
c7
s7
incen
c7
s7
incen
s7
s7
wren
c6
s6
wren
c6
s6
wren
s6
s6
BIT
NAME
incen
(1)
VALUE
MEANING
7
0
1
0
1
hold value of DRIVECURSEG
increment DRIVECURSEG at the end of each CD-ROM block received
enable writes of data transferred
disable write of data transferred
6
wren
(2)
ADDRESS
NAME
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FF0DH
FF0EH
FF0FH
CTRL0
CTRL1
CTRL2
decen
syien
modrq
ahead
syden
formrq
e01rq
asyn
autoform
cowren
automode
eramrq
onepass
mbckrq
wrreq
eccrq
dscren
encode
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