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參數(shù)資料
| 型號(hào)： | S82451KX |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP144 |
| 封裝： | QFP-144 |
| 文件頁(yè)數(shù)： | 40/180頁(yè) |
| 文件大?。?/td> | 1094K |
| 代理商： | S82451KX |
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126
PRELIMINARY
82453KX/GX, 82452KX/GX, 82451KX/GX (MC)
A
Table 22 provides a summary of the characteristics of memory configurations supported by the 450KX/GX MC.
Minimum values listed are obtained with single-sided SIMMs, and maximum values are obtained with double-
sided SIMMs.
Refresh Operation
Refresh for the memory array is handled automatically by the MC. The rate of refresh cycles is programmable
in the MEMTIM register (AC-AFh).
An alternative to a single refresh cycle is to stagger refreshes across the DRAM rows. Refresh stagger allows
the refresh power surge to be tailored to the system. This allows the system to select staggering of row
refreshes by one clock increments for zero to seven cycles. While refreshing fewer rows at once increases the
chance of a refresh request collision with a host request, it enables the system to handle the power surge
caused by refresh. Staggering refreshes within a group increases the time for the group refresh, but spreads
the power demands over time, and thus allows larger groups to be refreshed. Refresh Staggering provides
substantial power surge reduction over refreshing all rows simultaneously.
Table 22. Minimum and Maximum Memory Sizes for Each Configuration
Device
Non-Interleaved
2-Way Interleaved
4-Way Interleaved
Min (Inc)
Max
Min (Inc)
Max
Min (Inc)
Max
512k x 8
4 MB
16 MB
8 MB
32 MB
16 MB
128 MB
32 MB
64 MB
1M x 4
8 MB
32 MB
16 MB
64 MB
32 MB
256 MB
64 MB
128 MB
2M x 8
16 MB
64 MB
32 MB
128 MB
64 MB
512 MB
128 MB
256 MB
4M x 4
32 MB
128 MB
64 MB
256 MB
128 MB
1 GB
256 MB
512 MB
8M x 8
64 MB
256 MB
128 MB
512 MB
256 MB
2 GB
512 MB
1 GB
16M x 4
128 MB
512 MB
256 MB
1 GB
512 MB
4 GB
1 GB
2 GB
The 450GX MC does not support portions of the memory being 4-way interleaved and other portions being
non-interleaved or 2-way interleaved. The system does, however, support a 4-way or 2-way interleaved design
in which one interleave is populated (operates as a non-interleaved configuration) or a 4-way interleaved
design in which two interleaves are populated (operates as a 2-way configuration). There is no restriction on
which interleaves are populated to form a non-interleaved or 2-way interleaved configuration, as long as all
rows are populated in the same way.
For the 450GX, two MCs can be used in a system permitting a maximum of 8 Gbytes of main memory. When
two controllers are present in a system, the memory configuration and operation of an MC is independent of
the other MC. The OMCNUM signal determines the configuration address and the default base address of a
controller. Beyond this, the general behavior of each memory subsystem is identical.
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