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參數(shù)資料
| 型號： | S82451KX |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP144 |
| 封裝： | QFP-144 |
| 文件頁數(shù)： | 37/180頁 |
| 文件大?。?/td> | 1094K |
| 代理商： | S82451KX |
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PRELIMINARY
123
A
82453KX/GX, 82452KX/GX, 82451KX/GX (MC)
3.0
MC FUNCTIONAL DESCRIPTION
This section describes the MC functions and hardware interfaces including the Memory and I/O Mapping, Host
Bus Interface, DRAM Interface, and Clocks and Reset.
3.1
Memory and I/O Map
The MC provides the interface between the host bus and main memory. The processor memory space is 64
Gbytes (36-bit addressing). An MC can control up to 1 Gbyte of memory for the 450KX and 4 Gbytes of
memory for the 450GX. The MC registers that control memory space access are:
Programmable Attribute Map (PAM[6:0]) Registers. These registers provide Read Only, Write Only,
and Read/Write Disable for fixed memory regions in the PC compatibility area.
Video Buffer Area Enable (VBA) Register. This register enables the A0000–BFFFFh fixed region.
Low Memory Gap (LMG) Register. This register defines a hole in memory located from 1 to 4 Gbytes
on any 1 Mbyte boundary where accesses can be directed to the PCI bus (via the PB). The size can be
1, 2, 4, 8, 16, or 32 Mbytes. This gap must be located below the Memory Gap and High Memory Gap.
The Low Memory Gap is used by ISA devices such as LAN or linear frame buffers that are mapped into
the ISA Extended region, or by any EISA or PCI device.
Memory Gap Registers (MG and MGUA) Registers. These two registers define a hole in memory
located from 1 to 64 Gbytes on any 1 Mbyte boundary where accesses can be directed to the PCI bus
(via the PB). This gap (1, 2, 4, 8,16, or 32 Mbytes in size) must be located above the Low Memory Gap
and below the High Memory Gap areas. The Memory Gap is used by ISA devices (e.g., LAN or linear
frame buffers) that are mapped into the ISA Extended region, or by any EISA or PCI device.
High Memory Gap Registers (HMGSA and HMGEA) Registers. These two registers define a gap in
memory that can be located from 1 to 64 Gbytes on any 1 Mbyte boundary where accesses can be
directed to the PCI bus (via the PB). The size ranges from 1 Mbyte to 64 Gbytes. This gap must be
located above the Memory Gap and the Low Memory Gap areas. The High Memory Gap provides
additional support for memory mapped I/O.
SMMRAM Range (SMMR) Register and the SMMRAM Enable (SMME) Register (Only when
SMMEM# is asserted by the processor.). SM memory can overlap with memory residing on the host
bus or memory normally residing on the PCI bus. When the SM range is enabled, SM accesses are
handled by the MC. If the SMMEM# signal is not asserted, accesses to the MC’s enabled SM Range are
ignored (this allows the SM memory to overlap with memory normally residing on the host bus, since the
SMM Range may also be mapped through another MC range register). The RSMI# signal may be
asserted in the Response Phase by a device in SMM power-down mode. The MC does not assert this
signal.
NOTE:
Since leaving system management mode effectively remaps the system memory space, one must take
care with SMM memory that is cached. If SMMRAM is cast as writeback memory, a WBINVD instruction
must be executed immediately prior to the execution of the RSM instruction which exits SMM mode. This
will force all modified data to be written back while memory is still mapped for SMM.
Base Address (BASEADD) Register. An 82453GX responds to memory accesses between the
address programmed into this register and the calculated top of its memory range (calculated top of
MC memory address = base + memory size + Low Memory Gap size + Memory Gap size + High
Memory Gap size). Note that the DRAM memory behind the memory gaps can be reclaimed.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| S82452KX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Data Path Controller |
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| S82454KX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bus Interface/Controller |
| S8248P12NF | 功能描述:ANTENNA 824-896MHZ 8DBI N FML RoHS:是 類別:RF/IF 和 RFID >> RF 天線 系列:* 標準包裝:1 系列:* |
| S82510 DIE | 制造商:Intel 功能描述: |
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