
118
PRELIMINARY
82453KX/GX, 82452KX/GX, 82451KX/GX (MC)
A
12:11
RAS# Pulse Width (RASPW). This field selects the minimum cycles that RASx# is asserted.
RASPW should be set to the larger of the following values—(RCD + CAH + 1) or (RCD + WCAS - 1)
or (RCD +RCAS - 1)
Bits[12:11]
Cycles
00
4
01
5
10
6 (default)
11
7
10
Column Address Hold Time (CAH). 0=1 cycle. 1=2 cycles (default). CAH is the number of cycles
from the time CAS# is asserted to when the column address can be changed. Note that CAH must
be set to 1 cycle if RCAS=2 or RASPW minus RCD = 2.
9:8
Read CAS# Pulse Width (RCAS). Number of cycles CAS# is asserted for read cycles. RCAS must
be set to ensure data setup to the DP from CAS# asserted.
Bits[9:8]
Cycles
00
2
01
3 (default)
10
4
11
5
7:6
Write CAS# Pulse Width (WCAS). WCAS selects the number of cycles CAS# is asserted for write
cycles. See notes for LWC field description. WCAS should be set to RCAS or RCAS minus 1,
depending on data hold time requirements (see LWC field).
Bits[7:6]
Cycles
00
2 (default)
01
3
10
4
11
5
CAS# Precharge Time (CP). 0=1 cycle (default). 1=2 cycles. CP selects the number of cycles for
CAS# precharge. See notes for LWC field description.
4
RAS# to Column Address Delay (RCAD). RCAD selects the number of cycles from the time RAS#
is asserted to when Column address is asserted. 0 = 1 cycle. 1 = 2 cycles (default). RCAD must
equal 1 cycle if RCD equals 2 cycles.
3:2
RAS# to CAS# Delay (RCD). RCD selects the number of cycles from the time RAS# is asserted to
when CAS# is asserted.
Bits[3:2]
Cycles
00
Reserved
01
3 (default)
10
4
11
Reserved
1:0
RAS# Precharge Time (RP). RP selects the number of cycles for RAS# pre-charge.
Bits[1:0]
Cycles
00
3
01
4
10
5 (default)
11
6
Bits
Description