
PRELIMINARY
41
A
82454KX/GX (PB)
2.4.17 DCC—DETURBO COUNTER REGISTER
Address Offset:
51h
Default:
80h
Attribute:
Read/Write
In deturbo mode this register determines how many clocks BPRI# is asserted in order to throttle the host bus.
The host bus pipeline is stalled at a rate determined by this register. The Deturbo Counter value is compared to
an 8 bit counter running at the host bus clock (BCLK) divided by 8.
2.4.18 CRWC—CPU READ/WRITE CONTROL REGISTER
Address Offset:
53h
Default:
00h
Attribute:
Read/Write
This register enables/disables processor writes to PCI to be posted in the PB.
1:0
82454KX: Reserved. Must be set to 01.
Bits
Description
7:0
Deturbo Count Value. When the counter value is greater than this register value, BPRI# is
asserted by the PB. BPRI# is negated when the count value is less than or equal to this register
value. Smaller values in this register result in slower deturbo emulation speeds.
Bits
Description
7:2
Reserved.
1
Host-to-PCI Write (Outbound) Posting Enable. 1=Enable. 0=Disable.
0
Reserved.
Bits
Description
82454GX: Bridge Arbitration Mode. These bits determine the arbitration mode the PB uses before
taking ownership of the processor BPRI# signal.
Bits[1:0]
Function
00
No arbitration (single bridge system)
01
Arbitration mode (This PB provides the arbitration unit for an Auxiliary PB)
10
External arbiter mode. (This setting is for the Auxiliary bridge)
11
Reserved.
Note that, in a single PB system where the internal arbiter is not needed, this field should be
changed from its default value to 00.
For the 82454GX in a dual PB system, this register is only available in the Compatibility PB and is not available
in the Auxiliary PB.