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參數(shù)資料
| 型號(hào)： | S82451KX |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP144 |
| 封裝： | QFP-144 |
| 文件頁(yè)數(shù)： | 38/180頁(yè) |
| 文件大小： | 1094K |
| 代理商： | S82451KX |
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124
PRELIMINARY
82453KX/GX, 82452KX/GX, 82451KX/GX (MC)
A
High BIOS (HBIOS) Register. The 64 Kbyte region from F0000–FFFFFh is treated as a single block
and is normally Read/Write disabled in the MC(s) and Read/Write enabled in the PB. After power-on
reset, this region is R/W enabled in the PB (Compatibility PB only in the 450GX and R/W disabled in the
Auxiliary PB). Thus, the PB can respond to fetches during system initialization. The Read/Write
attributes for this region may be used in conjunction with the Read/Write attributes in the PB to “shadow”
BIOS into RAM.
I/O APIC Range (APICR) Register. This register provides an I/O APIC configuration space. There is no
I/O APIC in the PB or the MC.
DRAM Row Limit (DRL) Registers. These registers define the upper and lower addresses for each
DRAM row and represent the boundary addresses in 4 Mbyte granularity.
If a memory space access is in one of the above ranges, and that range is enabled for memory access, the MC
claims the transaction and becomes the response agent.
The MC performs memory recovery on gap ranges greater than or equal to 1 Mbyte that are created by the
Low Memory Gap, Memory Gap, and the High Memory Gap areas. This memory is relocated to the top of the
MC’s memory. The MC performs a subtraction of the size of the hole in the memory map to generate an
effective memory address.
Note that the PB (Compatibility PB in an 450GX dual PB system) is responsible for claiming any unclaimed
transactions on the host system bus. Therefore, any memory space access that is above the top of system
main memory is claimed by the PB.
The MC has two registers located in the processor’s I/O space (0CF8h and 0CFCh) that are used to configure
the MC. See the Register Descripiton section for details.
3.2
Host Bus Interface
The Pentium Pro processor bus provides an efficient, reliable interconnect between multiple Pentium Pro
processors and the PB and MC. The bus provides 36 bits of address, 64 bits of data, protection signals needed
to support data integrity, and the control signals to maintain a coherent shared memory in the presence of
multiple caches.
The Pentium Pro processor bus achieves high bus efficiency by providing support for multiple, pipelined trans-
actions and deferred replies. A single Pentium Pro processor may have up to four transactions outstanding at
the same time, and can be configured to support up to eight transactions active on the Pentium Pro processor
bus at any one time. The MC supports up to four transactions that target its associated memory space. The MC
contains read and write buffers for memory accesses.
For the 450GX, the base address for the MC that is not MC #0 must include the size of any memory gaps
programmed in the previous (or lower base address) MC.
There can be up to two MCs in a system permitting up to 8 Gbytes of system main memory. The portion of the
processor’s memory space controlled by an MC is determined by the Base Address Register and memory size.
In a PC architecture, the only restrictions on MC placement are that there be memory starting at address 0 and
that there be enough memory to operate a system. The MCs in a system need not have contiguous address
spaces. The High Memory Gap in one MC could be used to span the gap between the top of its memory map
and the base address of the other MC.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S82452KX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Data Path Controller |
| S82453KX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| S82454KX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bus Interface/Controller |
| S8248P12NF | 功能描述:ANTENNA 824-896MHZ 8DBI N FML RoHS:是 類別:RF/IF 和 RFID >> RF 天線 系列:* 標(biāo)準(zhǔn)包裝:1 系列:* |
| S82510 DIE | 制造商:Intel 功能描述: |
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