
34
PRELIMINARY
82454KX/GX (PB)
A
2.4.1
VID—VENDOR IDENTIFICATION REGISTER
Address Offset:
00–01h
Default:
8086h
Attribute:
Read Only
The VID Register contains the vendor identification number. This 16-bit register combined with the Device
Identification Register uniquely identify any PCI device. Writes to this register have no affect.
2.4.2
DID—DEVICE IDENTIFICATION REGISTER
Address Offset:
02–03h
Default:
84C4h
Attribute:
Read Only
This 16-bit register combined with the Vendor Identification Register uniquely identifies any PCI device. Writes
to this register have no affect.
2.4.3
PCICMD—PCI COMMAND REGISTER
Address Offset:
04–05h
Default:
0007h
Attribute:
Read/Write
This register controls the PB’s ability to respond to PCI cycles. See PCISTS Register for corresponding error
reporting. See ERRCMD Register (70h) for additional controls.
Bits
Description
15:00
Vendor Identification. This is a16-bit value (8086) assigned to Intel.
Bits
Description
15:00
Device Identification. This is a16-bit value (84C4) assigned to the PB.
Bits
Description
15:9
Reserved.
8
SERR# Enable. 1=Enable. 0=Disable. When enabled, the PB asserts SERR#, if the corresponding
bits in the ERRCMD Register are enabled.
7
Wait Cycle Control. (Not Implemented). This bit is hardwired to 0.
6
Parity Error Response Enable. 1=Enable PCI parity error checking (See ERRCMD Register for
generation of PERR# signal.). 0=Disable. Note that PCI parity errors will not be reported using
SERR# unless both this bit and bit 8 are set to 1.
5
Reserved.
4
Memory Write and Invalidate Enable. 1=Enable. 0=Disable. When disabled, Memory Write
commands are used.
3
Reserved.