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參數(shù)資料
| 型號(hào)： | S82451KX |
| 廠商： | INTEL CORP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP144 |
| 封裝： | QFP-144 |
| 文件頁(yè)數(shù)： | 113/180頁(yè) |
| 文件大?。?/td> | 1094K |
| 代理商： | S82451KX |
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30
PRELIMINARY
82454KX/GX (PB)
A
2.2.3
CONFDATA—CONFIGURATION DATA REGISTER
Address Offset:
0CFCh
Default:
00000000h
Attribute:
Read/Write
CONFDATA is a 32-bit read/write window into configuration space. The 32-bit portion of configuration space
that is referenced by CONFDATA is determined by the contents of CONFADD. The byte enables during the
0CFCh access select which bytes of the 32-bit window are updated.
2.3
PCI Configuration Space
The PB fully supports mechanism #1 for host accesses to PCI Configuration Space Registers (refer to the PCI
Specification for details on mechanism 1). The PB can perform three types of configuration cycles.
1. An internal access is performed if the Bus Number is 0, and the Device Number selects this PB. No PCI
cycles are generated.
2. A Type 0 translation is performed if the PCI device being configured is on this PB’s PCI bus (the Bus
Number matches the number in the PB’s PCI Bus Number register), and the Device Number is less than
or equal to 15.
3. A Type 1 translation is performed if the device being configured is on another hierarchical PCI bus below
the PB’s PCI bus (the Bus Number is between the PB’s PCI Bus Number and Subordinate PCI Bus
Number).
The PCI Configuration Space protocol requires that all PCI buses in a system be assigned a Bus Number.
Furthermore, bus numbers must be assigned in ascending order within hierarchical buses. Each bridge must
have a register that contains its PCI Bus Number and a register that contains its Subordinate PCI Bus Number.
The PCI Bus Number and Subordinate PCI Bus Number must be loaded by POST code. The Subordinate PCI
Bus Number is the bus number of the last hierarchical PCI bus under the current bridge. (The PCI Bus Number
and Subordinate PCI Bus Number are the same in the last hierarchical bridge.) At the top of the hierarchy, peer
bridges continue the ascending bus numbering scheme. Refer to the PCI specification for additional examples.
For the 450KX/GX, the implementation of the PCI configuration protocol logically maps the configuration
registers of the PB (and MC) to bus number 0. These devices, which are on the host bus, use Device Numbers
16 through 30 (Figure 2). Device numbers below 15 can be used on the PCI bus that uses bus number 0. This
allows a system to be designed with hierarchical PCI buses starting with bus number 0. All bridges have
programmable PCI bus numbers and programmable subordinate PCI bus numbers as described in the PCI
CSE protocol for dual PCI bridge systems. A PB’s bus number register should be programmed to the number of
the PCI bus immediately beneath it. However, the PB’s configuration registers remain at Bus number 0.
The PB is the response agent for CPU accesses to the CONFADD location. The MC snoops writes to this
location. The device selected by the CONFADD Register responds to CONFDATA accesses.
Bits
Description
31:0
Configuration Data Window. If bit 31 of CONFADD=1, an access to CONFDATA I/O space is
mapped to configuration space using the contents of CONFADD.
For the 82454GX, the Compatibility PB is the response agent for CPU accesses to the CONFADD location and
the Auxiliary PB as well as the MCs snoop writes to this location.
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