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參數(shù)資料
| 型號： | S82451KX |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP144 |
| 封裝： | QFP-144 |
| 文件頁數(shù)： | 146/180頁 |
| 文件大?。?/td> | 1094K |
| 代理商： | S82451KX |
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60
PRELIMINARY
82454KX/GX (PB)
A
3.2
Host Bus Interface
The Pentium Pro processor bus provides an efficient, reliable interconnect between multiple Pentium Pro
processors and the PB and MC. The bus provides 36 bits of address, 64 bits of data, protection signals needed
to support data integrity, and the control signals to maintain a coherent shared memory in the presence of
multiple caches.
The Pentium Pro processor bus achieves high bus efficiency by providing support for multiple, pipelined trans-
actions and deferred replies. A single Pentium Pro processor may have up to four transactions outstanding at
the same time, and can be configured to support a total of either one or eight transactions active on the
Pentium Pro processor bus at any one time. The PB supports up to eight active transactions on the host bus
(In-Order Queue depth of 8). During the host bus reset and configuration, all host bus devices are configured to
support either one or eight transactions in their In-Order Queue.
The number of transactions that can target a particular bus client is configured separately from the total number
of transactions allowed on the bus. The PB accepts up to four transactions into the Outbound Request Queue
that target its associated PCI bus.
The PB provides four 32-byte buffers for outbound data (host-to-PCI writes or PCI reads from the host bus),
and four 32-byte buffers for inbound data (PCI-to-host writes or CPU reads from PCI).
As a host bus master, the PB does not support deferred responses. The EXF1# extended function signal (Defer
Enable) will never be asserted for a host transaction initiated by the PB.
The host bus supports ECC over the data bus, and parity protection over the address, request, and response
lines. The PB generates and checks ECC over the data lines (82454GX only), and generates and checks parity
over the address and request/response signal lines (both 82454KX/GX). Note, ECC generation and checking
on the data lines and parity generation and checking on the request/response lines can be enabled or disabled
during system configuration.
NOTE:
1. The PB is a non-caching agent and does not participate in the Snoop phase. The Write Back (WB)
memory types can not be mapped through the PB (snoop write-back data is ignored by the PB for
implicit writebacks initiated by other agents). No WB memory types should be mapped to PCI. For PCI
Frame Buffers, the Write Combining (WC) memory type is recommended.
2. The PB is a non-caching agent; however all Pentium Pro processor commands are defined for the PB.
Therefore Read Invalidate transactions are treated as reads by the PB. Write Invalidate cycles are
treated as writes of length 0 by the PB. Write-backs initiated by other agents are ignored by the PB.
3. When the processor receives an SMI#, it invokes an SMI Acknowledge Transaction before entering the SMI handler
routine. The Compatibility PB generates the response phase for an SMI Acknowledge transaction and also asserts
the SMIACT# signal, if SMMEM# is asserted. Once asserted SMIACT# remains asserted until an SMI Acknowledge
transaction occurs with SMMEM# negated. The other System Management Mode transaction that is supported on the
processor interface is Stop Clock Acknowledge. The Stop Clock Acknowledge is an indication from the processor to
the system that the processor is powering down the internal caches to save power. For Stop Clock Acknowledge
Transactions, the Compatibility PB is the responding agent and generates a Stop Clock Grant special cycle on its PCI
bus.
4. If the SMRAM space is set up as writeback memory, A WBINVD instruction must be executed in the
SMM handler immediately before execution of the RSM instruction that exits SMM mode.
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相關代理商/技術參數(shù) |
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