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參數(shù)資料
| 型號： | S82451KX |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP144 |
| 封裝： | QFP-144 |
| 文件頁數(shù)： | 144/180頁 |
| 文件大?。?/td> | 1094K |
| 代理商： | S82451KX |
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58
PRELIMINARY
82454KX/GX (PB)
A
I/O APIC Range (APICR) Register. This register provides an I/O APIC configuration space. There is no
I/O APIC in the PB or the MC. Note that, the address range between the APIC configuration space and
the High BIOS range (FED00000h–FFDFFFFFh) is always mapped to local memory unless: 1) The
range is above top of physical memory or 2) The High BIOS and APIC ranges are disabled in the PB
and the range falls within a memory gap range.
PCI Frame Buffer (PFB) Register. The PCI Frame Buffer range can start on any 1 MByte boundary
from 1–4 Gbytes and can be 1, 2, 4, 8, 16,or 32 Mbytes.
SMM Range (SMMR) Register along with the SMM Enable (SMME) Register (only when SMMEM#
is asserted). A Pentium Pro processor asserts SMMEM# in its Request Phase if it is operating in
System Management Mode. The default SMRAM area is an address range that is normally mapped
through the PB to the PC compatible video graphics adapter. The PB ignores accesses to this overlaid
address range when the SMMR Register is enabled and SMMEM# is asserted during host bus transac-
tions.
SMM Support. The PB supports System Management Mode by allowing the SMRAM region in the MC to
overlay addresses that are normally mapped to the PCI bus. For cases where 64 Kbytes is insufficient for a
given application, SMRAM can be relocated by the SMMR Register to a different start address set in 64 Kbyte
increments and a maximum range of 1 Mbyte. The SMMR Register should also be used if the Top Of Memory
Register is enabled and SMRAM is placed above normal memory. The SMMR Register is programmed in this
instance to ignore the SMRAM range during SMMEM# accesses, but claim this range for normal accesses
(SMRAM Range overrides Top of Memory).
When the processor receives an SMI#, it invokes an SMI Acknowledge Transaction before entering the SMI
handler routine. The Compatibility PB generates the response phase for an SMI Acknowledge transaction and
also asserts the SMIACT# signal, if SMMEM# is asserted. Once asserted SMIACT# remains asserted until an
SMI Acknowledge transaction occurs with SMMEM# negated. See the Host Bus Interface section for additional
information on SMM mode.
Memory Mapped I/O. The PB allows memory addresses to be mapped to the host bus or to a PCI bus below
the PB. Memory mapped I/O devices can be located anywhere in the PB’s 64 Gbyte address space. The
Frame Buffer Range allows the PB to decode memory mapped I/O space extending up to 4 Gbytes. The
Memory Space Gap and High Memory Gap Registers allow the PB to decode two address ranges extending up
to 64 Gbytes.
Host Transactions to Memory Space. If a memory space address is in one of the above ranges, and that
range is enabled, the PB claims the transaction and forwards it to the PCI bus. Accesses that are not in one of
the enabled ranges and below the top of main memory are assumed to be accesses to main memory and are
not claimed by the PB. The PB (Compatibility PB in an 82454GX dual PB system) is responsible for any
unclaimed transactions on the host bus. Therefore, any memory space access that is above the top of main
memory is claimed by this PB and forwarded to its PCI bus, if enabled in the TSM Register. Otherwise, transac-
tions that are not mapped to any host bus device will time-out. Transactions that time-out on the host bus are
handled by the PB (Compatibility PB in an 82454GX dual PB system) to remove them from the In-Order
Queue. These transactions are not forwarded to PCI.
PCI Transactions to Memory Space. All PCI memory space accesses below the top of main memory (as
programmed in the TSM Register) are forwarded to the host bus, unless they are specifically directed to PCI by
one of the memory space access registers listed at the beginning of this section.
In a dual PB system, the Compatibility and Auxiliary PB default to forwarding all PCI memory space accesses
above the top of memory to the host bus.
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