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參數(shù)資料
| 型號(hào)： | S82451KX |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP144 |
| 封裝： | QFP-144 |
| 文件頁(yè)數(shù)： | 30/180頁(yè) |
| 文件大?。?/td> | 1094K |
| 代理商： | S82451KX |
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PRELIMINARY
117
A
82453KX/GX, 82452KX/GX, 82451KX/GX (MC)
On reset, the Memory Timing Register fields are set to values that allow operation in the range 50 MHz to 66
MHz with 70 ns DRAMs. The refresh counter is set such that refreshes occur assuming that the operating
frequency is 50 MHz, which is faster than required at 60 or 66 MHz. All other parameters are set assuming that
the operating frequency is 66 MHz which adds more clocks than required if the real frequency is 60 MHz. For
optimal performance, the values in this register may have to be reprogrammed after reset.
Bits
Description
31
Reserved.
30:20
Refresh Count (in cycles) (REFRC). The refresh counter must be set so that refreshes occur often
enough that the entire DRAM array is refreshed before DRAM data loss occurs. The eleven bit
counter can be programmed from 1 to 2047. The counter time base is equal to one system clock
period (15 ns for a 66 MHz clock, etc.). The value is chosen to give a refresh every 15.625 usec (or
less). For example, 30Dh=15.620 usec at 50 MHz (default) and 411h = 15.615 usec at 66 MHz
19:17
Refresh Stagger (REFRS). The refresh stagger sets the time, in clock cycles, from the start of one
row’s refresh to the start of the next row’s refresh. Refresh in the DRAMs causes the DRAMs to
become active which draws considerable power. Refreshing all rows at once may not be possible for
the system power supply. The refresh stagger field of the memory timing register allows the power
surge to be spread evenly across the refresh cycle. The amount of time necessary to stagger the
refreshes is system design and DRAM memory type dependent. 000=All rows refreshed at once.
Bits[19:17]
Stagger
Bits[19:17]
Stagger
000
0 cycles
100
4 cycles
001
1 cycle
101
5 cycles
010
2 cycles
110
6 cycles
011
3 cycles
111
7 cycles (default)
16
Refresh Enable (REFRE). 1=Enable (default). 0=Disable.
15
CAS# Setup Time To RAS# for CAS-Before-RAS Refresh Cycles. 1=1 Cycles. 0=2 Cycle
(default). Typically, 1 cycle is sufficient. However, in some cases the combination of DRAM timings,
clock speed, and system level skew between CASx# and RASx# may require 2 cycles.
14:13
Last Write to CAS# (LWC). Number of cycles from when the last data is asserted to the MIC to
when CAS# is asserted. This determines data setup time before CAS# (i.e., data is driven for LWC
cycles, but delayed by one cycle).
Bits[14:13]
Cycles
00
Reserved
01
2 (default)
10
3
11
4
NOTES:
1. Write data setup time to CAS# asserted is LWC minus 1.
2. Write data hold time from CAS# asserted is 1 cycle if WCAS (bits[7:6]) equals 2 and is 2 cycles if
WCAS is greater than 2.
3. The following are the legal combinations of the WCAS, LWC, and CP fields for non-interleaved
and 2-way interleaved memory configurations. There are no restrictions for 4-way interleaved.
WCAS
LWC
CP
WCAS
LWC
CP
22
1,2
4
2
1,2
23
2
4
3
1,2
32
1,2
4
2
33
2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S82452KX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Data Path Controller |
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