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參數(shù)資料
| 型號(hào)： | S82451KX |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP144 |
| 封裝： | QFP-144 |
| 文件頁(yè)數(shù)： | 110/180頁(yè) |
| 文件大?。?/td> | 1094K |
| 代理商： | S82451KX |
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PRELIMINARY
27
A
82454KX/GX (PB)
The bridge that is in the path to the Boot ROM is always the PB with device number=11001, and is referred to
as the Compatibility PB. The Compatibility PB always decodes BIOS addresses after power-on reset.
NOTE:
When the address decode ranges of the 450KX/GX devices are being updated, no other host bus traffic is
allowed. This means that the code that updates initial configuration must be non-cached (to prevent speculative
reads). Further, in a multiprocessor system, precautions should be taken to assure that only one CPU is
accessing configuration space at a time.
2.2
I/O Space Registers
The PB has three registers located in I/O Space—the Configuration Address (CONFADD) Register, the Turbo
and Reset Control (TRC) Register, and the Configuration Data (CONFDATA) Register.
The CONFADD and CONFDATA Registers provide a window into the PB’s configuration space registers (see
Section 2.3 for additional details). A specific PCI bus, device, and register are selected by writing to the
CONFADD Register. Data is read from or written to the selected register by accessing the CONFDATA
Register. Note that the CONFADD Register is only selected by DWord accesses to CF8h. This allows the
CONFADD Register to overlap other byte registers (e.g., the TRC Register at CF9h). The CONFDATA Register
is not selected unless configuration accesses are enabled in the CONFADD Register. This allows the
CONFDATA Register to overlap other registers as well.
Table 7. I/O Space Registers
I/O Address
Mnemonic
Register Name
Access
CF8h
CONFADD
Configuration Address
R/W
CF9h
TRC
Turbo and Reset Control (Compatibility PB only)
R/W
CFCh
CONFDATA
Configuration Data
R/W
Note that in a dual PB system (82454GX only), the TRC Register is only in the Compatibility PB and the
Auxiliary PB ignores this address.
相關(guān)PDF資料 |
PDF描述 |
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| S83296SA | 16-BIT, MROM, 40 MHz, MICROCONTROLLER, PQFP100 |
| SB83296SA | 16-BIT, MROM, 40 MHz, MICROCONTROLLER, PQFP100 |
| S83C196MH | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80 |
| S83C51FB-BB44 | 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP44 |
| S83C51FC-5B44 | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S82452KX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Data Path Controller |
| S82453KX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| S82454KX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bus Interface/Controller |
| S8248P12NF | 功能描述:ANTENNA 824-896MHZ 8DBI N FML RoHS:是 類別:RF/IF 和 RFID >> RF 天線 系列:* 標(biāo)準(zhǔn)包裝:1 系列:* |
| S82510 DIE | 制造商:Intel 功能描述: |
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