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參數(shù)資料
| 型號： | S82451KX |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP144 |
| 封裝： | QFP-144 |
| 文件頁數(shù)： | 109/180頁 |
| 文件大?。?/td> | 1094K |
| 代理商： | S82451KX |
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26
PRELIMINARY
82454KX/GX (PB)
A
2.0
PB REGISTER DESCRIPTION
The PB contains two sets of registers (I/O space registers and PCI configuration registers) that are accessed
via the host CPU I/O address space. The I/O space registers provide access to the PCI configuration registers
through an indirect address scheme.
The PB internal registers (both I/O space registers and PCI configuration registers) are only accessible by the
host bus and cannot be directly accessed by PCI masters. The registers can be accessed as Byte, Word (16-
bit), or Dword (32-bit) quantities, with the exception of CONFADD which can only be accessed as a Dword. The
following nomenclature is used for access attributes.
RO
Read Only. If a register is read only, writes to this register have no effect.
R/W
Read/Write. A register with this attribute can be read and written.
R/WC
Read/Write Clear. A register bit with this attribute can be read and written. However, a write of
a 1 clears (sets to 0) the corresponding bit and a write of a 0 has no effect.
Some of the PB registers contain reserved bits. Software must deal correctly with fields that are reserved. On
reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any
particular value. On writes, unless otherwise specified in the individual register descriptions, software must
ensure that the values of reserved bit positions are preserved. That is, the values of reserved bit positions must
first be read, merged with new values for other bit positions and written back. In some cases, software must
program reserved bit positions to a particular value. This value is defined in the individual bit descriptions.
In addition to reserved bits within a register, the PB contains address locations in the PCI configuration space
that are marked “Reserved”. The PB responds to accesses to these address locations by completing the host
transaction. Software should not write to reserved PB configuration locations in the device-specific region
(above address offset 3Fh).
If RESET# is asserted (via either a power-on reset or by programming the TRC Register), the PB initializes its
registers to the default value (except for the BDNUM and CONFVR Registers). The default state represents
the minimum functionality feature set required to successfully bring up the system. Hence, it does not represent
the optimal system configuration. It is the responsibility of the system initialization software (usually BIOS) to
properly determine the operating parameters and optional system features that are applicable, and to program
the PB registers accordingly. The PB (Compatibility PB in an 450GX system) can generate a programmed hard
reset via the TRC Register.
2.1
Initialization and Configuration
The PB (and MC) contain a configuration space that uses the same access mechanism as described in the PCI
bus specification. With the exception of address decoding for BIOS accesses, the PB does not respond to host-
initiated memory accesses until the associated registers are initialized. The device number for the PB is
hardwired to 11001 for the 82454KX.
In dual PB systems, during a hard reset (via a power-on hard reset or by programming the Compatibility PB’s
TRC Register), both PBs set their internal configuration registers to predetermined default conditions.
For dual PB systems, there are two PB configurations (Compatibility and Auxiliary PB). These configurations
are defined by values on the IOGNT# and IOREQ# signal lines (high or low voltage levels) on the rising edge
of PWRGD. The values on IOGNT# and IOREQ# define the PB Identification (PBID) and are reported in the
DBNUM Register (offset 49h). Physical connections for the IOGNT# and IOREQ# signals are shown in the
Section 3.5. The PBID value defines the lower two bits of the five-bit device number.
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