
110
PRELIMINARY
82453KX/GX, 82452KX/GX, 82451KX/GX (MC)
A
2.3.10 SMME—SMRAM ENABLE REGISTER
Address Offset:
57h
Default:
00h
Attribute:
Read/Write
This register enables/disables the SMM range specified in the SMMR Register.
2.3.11 VBRE—VIDEO BUFFER REGION ENABLE REGISTER
Address Offset:
58h
Default:
00h
Attribute:
Read/Write
This register enables/disables the video buffer area.
2.3.12 PAM[0:6]—PROGRAMMABLE ATTRIBUTE MAP REGISTERS
Address Offset:
PAM0 (59h)—PAM6 (5Fh)
Default:
PAM0=03h, PAM[1:6]=00h
Attribute:
Read/Write
These seven registers select read only (RE=1, WE=0), write only (RE=0, WE=1), or read/write (RE=1, WE=1)
access attributes for 14 memory regions between the 512 Kbyte and 1 Mbyte address range. The individual
memory regions can also be disabled (RE=0, WE=0). Each register controls two regions; bits [7:4] control one
region and bits [3:0] control the other region. Note that the default for the 512–640 Kbyte region is read/write
enabled. The default for all other regions is read/write disabled.
Note that the PB has corresponding PAM registers. Only one device (MC/PB) should have the same space
enabled at one time to avoid access conflicts
Read Enable (RE)
When RE=1 (enabled), CPU read accesses to the corresponding memory region are
directed to main memory. When RE=0 (disabled), CPU read accesses are ignored.
Write Enable (WE)
When WE=1 (enabled), CPU write accesses to the corresponding memory region are
directed to main memory. When WE=0 (disabled), CPU write accesses are ignored.
Bits
Description
7:4
Reserved.
3
SMM RAM Enable. 1=Enable. 0=Disable.
2:0
Reserved.
Bits
Description
7:2
Reserved.
1
Video Buffer Area Enable (A0000–BFFFFh). 1=Enable. 0=Disable.
0
Reserved.