
PRELIMINARY
45
A
82454KX/GX (PB)
2.4.23 ERRCMD—ERROR REPORTING COMMAND REGISTER
Address Offset:
70h
Default:
00h
Attribute:
Read/Write
This register provides control for generating PCI SERR# and PERR# error signals. Note that for bits[7:4],
SERR# must be enabled in the PCICMD Register. For bit 3, PCI parity error checking must be enabled in the
PCICMD Register.
2.4.24 ERRSTS—ERROR REPORTING STATUS REGISTER
Address Offset:
71h
Default:
00h
Attribute:
Read/Write Clear
This register reports certain PCI data and address parity errors and for detection of a CPU shutdown cycle.
Software sets these bits to 0 by writing a 1 to them.
Bits
Description
7
SERR# on Receiving Target Abort (PB is PCI bus master). 1=Enable. 0=Disable.
6
SERR# on Transmitted Data Parity Error (Detected via PERR#). 1=Enable. 0=Disable.
5
SERR# on Received Data Parity Error (Detected via PAR). 1=Enable. 0=Disable. The PB is the
master.
4
SERR# on Address Parity Error Enable. 1=Enable. 0=Disable.
3
PERR# on Data Parity Error Enable. 1=Enable. 0=Disable. The received data can be the result of
a PB read or another PCI master write to the PB.
2:0
Reserved.
Bits
Description
7
Reserved.
6
PCI Data Parity Error When Writing PCI Data (PERR# was asserted). 1=Detected parity error.
5
Data Parity Error When Reading PCI Data (PAR was incorrect). 1=Detected parity error.
4
Detected PCI Address Parity Error. 1=PAR was incorrect when receiving address and C/BE[3:0]#
from another PCI master.
3:1
Reserved.
0
Shutdown Cycle from Host Bus Detected. 1=Detected. The PB optionally asserts INIT# as per
the setting in the PBC register (4Ch).
For the 82454GX in a dual PB system, this bit is only used in the Compatibility PB and is not
used in the Auxiliary PB.