
PRELIMINARY
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A
Contents
Chapter 1
Intel 450KX/GX PCIset Overview
1.0 Intel 450KX PCIset ....................................................................................................................................5
2.0 Intel 450GX PCIset ....................................................................................................................................6
3.0 Host Bus Efficiency ..................................................................................................................................6
4.0 System Memory Map ................................................................................................................................7
4.1 Compatibility Area ...............................................................................................................................8
4.2 Extended Memory (ISA) .....................................................................................................................9
4.3 Extended Memory (EISA) .................................................................................................................10
4.4 Extended Memory (above 4 Gbytes) ................................................................................................12
4.5 System Management Mode (SMM) ..................................................................................................12
5.0 I/O Space (PB Only) ................................................................................................................................12
6.0 Memory Mapped I/O ...............................................................................................................................13
Chapter 2
82454KX/GX PCI Bridge (PB)
1.0 PB Signal Descriptions ..........................................................................................................................19
1.1 PB Signals .......................................................................................................................................19
1.2 Signal State During Reset ................................................................................................................25
2.0 PB Register Description ........................................................................................................................26
2.1 Initialization and Configuration ..........................................................................................................26
2.2 I/O Space Registers ..........................................................................................................................27
2.2.1 CONFADD—Configuration Address Register ........................................................................28
2.2.2 TRC—Turbo and Reset ControL ............................................................................................29
2.2.3 CONFDATA—Configuration Data Register ............................................................................30
2.3 PCI Configuration Space ..................................................................................................................30
2.4 PB PCI Configuration Registers .......................................................................................................32
2.4.1 VID—Vendor Identification Register .......................................................................................34
2.4.2 DID—Device Identification Register .......................................................................................34
2.4.3 PCICMD—PCI Command Register .......................................................................................34
2.4.4 PCISTS—PCI Status Register ...............................................................................................35
2.4.5 RID—Revision Identification Register ....................................................................................36
2.4.6 CLASSC—Class Code Register ............................................................................................36
2.4.7 CLSIZE—Cache Line Size Register ......................................................................................36
2.4.8 PLTMR—PCI Latency Timer ..................................................................................................37
2.4.9 HEADT—Header Type Register .............................................................................................37
2.4.10 BIST—Bist register ..............................................................................................................37
2.4.11 TSM—Top of System Memory Register ...............................................................................38
2.4.12 PDM—PCI Decode Mode ....................................................................................................38