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參數(shù)資料
| 型號： | S5935 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PCI 5V Bus Master/Target Device 32-bit |
| 中文描述： | 5V的的PCI總線主/目標(biāo)設(shè)備的32位 |
| 文件頁數(shù)： | 86/190頁 |
| 文件大?。?/td> | 748K |
| 代理商： | S5935 |
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6-78
INITIALIZATION
S5935
LOADING FROM SERIAL NV MEMORIES
SNV tied high indicates that a serial nv memory (or
no external device) is present. When serial nv memo-
ries are used, data transfer is performed through a
two-wire, bidirectional data transfer protocol as de-
fined by commercial serial EEPROM/Flash offerings.
These devices have the advantages of low pin
counts, small package size, and economical price.
A serial nv memory is considered valid if the first
serial accesses contain the correct per-byte acknowl-
edgments (see Figure 3). If the serial per-byte ac-
knowledgment is not observed, the S5935
determines that no external serial nv memory is
present and the AMCC default Configuration Register
values are used.
Two pins are used to transfer data between the
S5935 PCI controller and the external serial memory:
a serial clock pin, SCL, and a serial data pin, SDA.
The serial clock pin is an output from the S5935, and
the serial data pin is bidirectional. The serial clock is
derived by dividing the PCI bus clock by 512. This
means that the frequency of the serial clock is ap-
proximately 65 kHz for a 33-MHz PCI bus clock.
Note: When a serial boot device is used, EA9 is de-
fined as a SCL divide by control pin.
If EA9 = 1 then SCL = PCLK/512
If EA9 = 0 then SCL = PCLK/8
This pin should be pulled high.
Table 1. Valid External Boot Memory Contents
Address
0040h-41h
0050h
0051
0052h
0053h
Data
not FFFFh
C2h, C1h or C0h
FFh
E8h
10h
Notes
This is the location that the S5933 PCI
Controller will load a customized vendor ID.
(FFFFh is an illegal vendor ID.)
This is the least significant byte of the region which
initializes the base address register #0 of the S5933
configuration register (Section 3.11). A value of C1h
assigns the 16 DWORD locations of the PCI operation
registers into I/O space, a value of C0h defines
memory space, a value of C2h defines memory space
below 1 Mbyte.
Required.
Required.
Required.
Communications with the serial memory involve sev-
eral clock transitions. A start event signals the
beginning of a transaction and is immediately fol-
lowed by an address transfer. Each address/data
transfer consists of 8 bits of information followed by a
1-bit acknowledgment. When the exchange is com-
plete, a stop event is issued. Figure 1 shows the
unique relationship defining both a start and stop
event. Figure 2 shows the required timing for ad-
dress/data with respect to the serial clock.
For random accesses, the sequence involves one
clock to define the start of the sequence, eight clocks
to send the slave address and read/write command,
followed by a one-clock acknowledge, and so on. Fig-
ure 3 shows the sequence for a random write access
requiring 29 serial clock transitions. At the clock speed
for the S5935, this corresponds to one byte of data
transferred approximately every 0.5 milliseconds. Read
accesses may be either random or sequential. Ran-
dom read access requires a dummy write to load the
word address and require 39 serial clock transitions.
Figure 4 shows the sequence for a random byte read.
To initialize the S5935 controller’s PCI Configuration
Registers, the smallest serial device necessary is a
128 x 8 organization. Although the S5935 controller
only requires 64 bytes, these bytes must begin at a
64-byte address offset (0040h through 007Fh). This
offset constraint permits the configuration image to
be shared with a memory containing expansion BIOS
code and the necessary preamble to identify an ex-
pansion BIOS. The largest serial device which may
be used is 2 Kbytes.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S5935QF | PCI 5V Bus Master/Target Device 32-bit |
| S5990-01 | POSITION SENSITIVE DETECTOR |
| S5629-01 | POSITION SENSITIVE DETECTOR |
| S5629-02 | POSITION SENSITIVE DETECTOR |
| S5991-01 | POSITION SENSITIVE DETECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S5935_07 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S59355QRC | 制造商:AppliedMicro 功能描述: |
| S5935QF | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935QRC | 制造商:AppliedMicro 功能描述:PCI Master Device 160-Pin PQFP |
| S5935TF | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI 5V Bus Master/Target Device 32-bit |
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