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參數(shù)資料
| 型號： | S5935 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PCI 5V Bus Master/Target Device 32-bit |
| 中文描述： | 5V的的PCI總線主/目標設(shè)備的32位 |
| 文件頁數(shù)： | 156/190頁 |
| 文件大?。?/td> | 748K |
| 代理商： | S5935 |
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11-148
PASS-THRU OVERVIEW
S5935
could remain asserted, indicating a burst read, but
the retry request conditions are identical for a single
data phase read and the first data phase of a burst
read.
BPCLK is identical to PCICLK, lagging by a propaga-
tion delay of a few nanoseconds (see Chapter 13).
PTATN# is asserted on the Add-On interface as soon
as FRAME# is sampled active at a PCICLK rising
edge.
After PTATN# is asserted, PTRDY# must be as-
serted by the 15th BPCLK rising edge to prevent the
S5935 from requesting a retry. TRDY# is asserted on
the PCI interface one clock cycle after PTRDY# is
asserted on the Add-On interface. If Add-On logic
does not return PTRDY# by the 15th BPCLK rising
edge, the S5935 asserts STOP#, requesting a retry
from the PCI initiator.
For Pass-Thru write operations, the S5935 never dis-
connects on the first or second PCI data phases of a
burst. The first data and second phases are always
accepted immediately by the S5935. No further ac-
tion is required by the PCI initiator. The only situation
where the S5935 may respond to a Pass-Thru write
with a retry request is after the second data phase of
a Pass-Thru burst write.
Figure 9 shows the conditions required for the S5935
to request a retry after the second data phase of a
burst transfer. This figure applies to both Pass-Thru
burst read and write operations.
The previous data phase is completed with the asser-
tion of PTRDY# at the rising edge of BPCLK 0. Add-
On logic must assert PTRDY# by the rising edge of
BPCLK 8 to prevent the S5935 from asserting
STOP#, requesting a retry. Meeting this condition al-
lows the S5935 to assert TRDY# by the rising edge
of PCICLK 8, completing the data phase with requir-
ing a retry.
When the S5935 requests a retry, the Pass-Thru sta-
tus indicators remain valid (allowing the Add-On logic
to complete the access). PTBURST# is the exception
to this. PTBURST# is deasserted to indicate that
there is currently no burst in progress on the PCI bus.
The other Pass-Thru status indicators remain valid
until PTATN# is deasserted. Figure 10 shows the
Add-On bus interface signals after the S5935 re-
quests a retry.
As long as PTATN# remains asserted, Add-On logic
should continue to transfer data. For PCI read opera-
tions, one Add-On write operation is required after a
retry request. After the Add-On write, asserting
PTRDY# deasserts PTATN#.
For Pass-Thru write operations, one or two data
transfers may remain after the S5935 signals a retry.
Two data transfers are possible because the S5935
has a double buffered Pass-Thru data register used
for writes. A PCI burst may have filled both registers
before the S5935 requested a retry. PTATN# re-
mains asserted until both are emptied. PTRDY# must
be asserted after each read from the Pass-Thru data
register. If both registers are full, PTATN# is
deasserted only after PTRDY# is asserted the sec-
ond time. The S5935 only accepts further PCI ac-
cesses after both registers are emptied.
8-Bit and 16-Bit Pass-Thru Add-On Bus Interface
The S5935 allows a simple interface to devices with
8-bit or 16-bit data buses. Each Pass-Thru region
may be defined as 8-, 16-, or 32-bits, depending on
the contents of the nv memory boot device loaded
into the PCI Base Address Configuration Registers
during initialization. The Pass-Thru Add-On interface
internally controls byte lane steering to allow access
to the 32-bit Pass-Thru Data Register (APTD) from 8-
bit or 16-bit Add-On buses.
Figure 9. Target Requested Retry after the First Data Phase of a Burst Operation
8
7
6
1
9
8
7
2
1
0
PCICLK
FRAME#
STOP#
BPCLK
PTATN#
PTRDY#
Latest assertion of PTRDY#
to prevent disconnect
PTRDY# asserted too late,
results in disconnect
PCI Data Transfer
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S5935QF | PCI 5V Bus Master/Target Device 32-bit |
| S5990-01 | POSITION SENSITIVE DETECTOR |
| S5629-01 | POSITION SENSITIVE DETECTOR |
| S5629-02 | POSITION SENSITIVE DETECTOR |
| S5991-01 | POSITION SENSITIVE DETECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S5935_07 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S59355QRC | 制造商:AppliedMicro 功能描述: |
| S5935QF | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935QRC | 制造商:AppliedMicro 功能描述:PCI Master Device 160-Pin PQFP |
| S5935TF | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI 5V Bus Master/Target Device 32-bit |
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